Matching filter calculating correlation valve utilizing exclusive-or of two data and exclusive-or of two codes corresponding to the input data

• US 6,724,812 B2
• Filed: 11/30/2000
• Issued: 04/20/2004
• Est. Priority Date: 11/30/1999
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Sato, Yuichi, Toyoyama, Shinji
• Primary Examiner(s): Ghayour, Mohammad H.
• Application Number:
  US09/725,763
• Publication Number:
  US 20010009575A1
• Time in Patent Office: 1,237 Days
• Field of Search: 375/152, 375/207, 375/150, 708/3
• US Class Current: 375/152
• CPC Class Codes: H04B 1/7093 Matched filter type

Abstract

A matched filter has a circuit calculating an exclusive-OR of two input data, a circuit calculating an exclusive-OR of two codes corresponding to the two input data, respectively, and a correlation processor. The correlation processor, using the exclusive-OR of the two input data, one of the two input data, the exclusive-OR of the two codes, and the code corresponding to one of the two input data, calculates a correlation value of the two input data and the two codes.

Claims

1. A matched filter for calculating a correlation value between an input data sequence of a specified length and a code sequence of a specified length, comprising:

a circuit calculating an exclusive-OR of an input data and a delayed input data;

a circuit calculating an exclusive-OR of two codes corresponding to the two input data, respectively; and

a correlation calculating means that, using the exclusive-OR of the two input data, one of the two input data, the exclusive-OR of the two codes, and the code corresponding to one of the two input data, calculates a correlation value of the input data and the two codes.

2. The matched filter according to claim 1, wherein said correlation calculating means calculates correlation values for a plurality of pairs of input data, said plurality of pairs of input data including at least one pair of consecutive input data.

3. The matched filter according to claim 1, wherein

said circuit calculating an exclusive-OR of two input data includes a plurality of circuits associated with each other to calculate an exclusive-OR of two input data in each of a plurality of pairs;

said circuit calculating an exclusive-OR or two codes includes a corresponding to two input data in a pair, and wherein

said correlation calculating means comprises a plurality of correlation processor circuits each calculating a correlation value of two input data in a pair and two codes corresponding to the two input data, using the exclusive-OR of the two input data, one of the two input data, the exclusive-OR of the two codes, and the code corresponding to one of the two input data.

4. The matched filter according to claim 2, wherein said plurality of pairs of input data include two or more sequential pairs each consisting of two consecutive input data, the two consecutive input data in one pair and the two consecutive input data in a next pair also constitute consecutive input data, and said correlation calculating means sequentially use the calculated exclusive-Ors of the pairs of consecutive two input data for the calculation of the correlation values.

5. The matched filter according to claim 4, wherein each of said plurality of pairs of input data consists of two consecutive input data.

6. The matched filter according to claim 1, wherein the exclusive-OR of the two input data and the one of the two input data are delayed by different delay systems.

7. The matched filter according to claim 6, wherein each delay system includes delay elements, and a single clock is used for delay elements subsequent to an initial delay element of each delay system.

8. The matched filter according to claim 6, wherein each delay system includes delay elements, and an initial delay element of at least one delay system is supplied with a result of a logic operation of outputs from other delay elements.

9. The matched filter according to claim 6, wherein said delay systems include two or more delay systems delaying the exclusive-OR of the two input data and/or two or more delay systems delaying the one of the two input data.

10. The matched filter according to claim 1, wherein said correlation calculating means includes:

an operation means calculating an exclusive-OR of the exclusive-OR of the two input data and the exclusive-OR of the two codes corresponding to the two input data.

11. The matched filter according to claim 10, wherein said operation means comprise a plurality of exclusive-OR circuits.

12. The matched filter according to claim 8, further comprising a selector provided with a binary select signal, wherein

when the select signal is of a first binary value, said selector supplies an exclusive-OR delay element, for delaying the exclusive-OR of the two input data, with an exclusive-OR of a delayed one of the two input data and an input data, or

when the select signal is a second binary value different from the first binary value, said selector supplies the exclusive-OR delay element with an exclusive-OR of an input data and a result of an exclusive-OR of the output of a delay element of the delay system for the input data and of a delay element of the delay system for the exclusive-OR delay elements.

13. A matched filter for calculating a correlation value between an input data sequence of a specified length and a code sequence of a specified length, comprising:

an input data circuit calculating an exclusive-OR of two input data, wherein

said input data circuit includes a first delay system and at least a second delay system, the first delay system having a plurality of delay elements connected in series, and the second delay system having a plurality of delay elements connected in series;

said second delay system is provided with an associated second input circuit, wherein

said second input circuit includes a first exclusive-OR circuit, a second exclusive-OR circuit, and a selector,

said first exclusive-OR circuit calculates an exclusive-OR of an output of an initial delay element of said first delay system and an input data,

said second exclusive-OR circuit calculates an exclusive-OR of an input data and a result of an exclusive-OR of outputs of said first delay system and said second delay system,

said selector selects between the output of said first exclusive-OR circuit and said second exclusive-OR circuit based on a select signal and supplies the resulting selected signal to an initial delay element of said second delay system;

a circuit calculating an exclusive-OR of two codes corresponding to the two input data, respectively; and

a correlation calculation means that, using the output of the initial delay element of the first delay system, the output of the initial delay element of the second delay system, the exclusive-OR of the two codes, and the code corresponding to one of the two input data, calculates a correlation value of the two input data and the two codes.

14. The matched filter according to claim 13, wherein said selector is provided with a binary select signal, wherein

when the select signal is of a first binary value, said selector supplies a result of an exclusive-OR operation using a delayed input data and an input data, or

when the select signal is a second binary value different from the first binary value, said selector supplies a result of an exclusive-OR operation of an exclusive-OR of outputs from the first delay system and the second delay system, and the input data.