Method and system for exclusive two-level caching in a chip-multiprocessor
First Claim
1. A method for exclusive two-level caching in a chip-multiprocessor;
- comprising;
relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy;
providing a first tag-state structure in a first level cache of the two-level cache system, the first tag-state structure having state information;
maintaining in a second-level cache of the two-level cache system a duplicate of the first tag-state structure;
extending the state information in the duplicate of the first tag-state structure, but not in the first tag-state structure, to include an owner indication;
providing in the second-level cache a second tag-state structure so that a simultaneous lookup at the duplicate of the first tag-state structure and the second tag-state structure is possible; and
at any given time of a cache line lifetime in the chip-multiprocessor, associating a single owner with the cache line.
5 Assignments
0 Petitions
Accused Products
Abstract
To maximize the effective use of on-chip cache, a method and system for exclusive two-level caching in a chip-multiprocessor are provided. The exclusive two-level caching in accordance with the present invention involves method relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy. Additionally, the exclusive two-level caching involves providing a first-level tag-state structure in a first-level cache of the two-level cache system. The first tag-state structure has state information. The exclusive two-level caching also involves maintaining in a second-level cache of the two-level cache system a duplicate of the first-level tag-state structure and extending the state information in the duplicate of the first tag-state structure, but not in the first-level tag-state structure itself, to include an owner indication. The exclusive two-level caching further involves providing in the second-level cache a second tag-state structure so that a simultaneous lookup at the duplicate of the first tag-state structure and the second tag-state structure is possible. Moreover, the exclusive two-level caching involves associating a single owner with a cache line at any given time of its lifetime in the chip-multiprocessor.
-
Citations
18 Claims
-
1. A method for exclusive two-level caching in a chip-multiprocessor;
- comprising;
relaxing the inclusion requirement in a two-level cache system in order to form an exclusive cache hierarchy;
providing a first tag-state structure in a first level cache of the two-level cache system, the first tag-state structure having state information;
maintaining in a second-level cache of the two-level cache system a duplicate of the first tag-state structure;
extending the state information in the duplicate of the first tag-state structure, but not in the first tag-state structure, to include an owner indication;
providing in the second-level cache a second tag-state structure so that a simultaneous lookup at the duplicate of the first tag-state structure and the second tag-state structure is possible; and
at any given time of a cache line lifetime in the chip-multiprocessor, associating a single owner with the cache line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
determining which instance of one or more copies of a particular cache is the owner copy of that cache line by using information obtained from the simultaneous lookup respecting that cache line.
- comprising;
-
7. A method as in claim 1, wherein the simultaneous lookup respecting a particular cache line yields the state information of one or more instances of the particular cache line that are present in the first-level cache and/or the second-level cache, the state information for each instance of that cache line including its owner state, and wherein the owner state of only one instance is owner.
-
8. A method as in claim 1, wherein if the substantially simultaneous lookup yield no instance of the particular cache line in the first-level cache which is owner, the instance in second-level cache is owner by default.
-
9. A method as in claim 1, wherein associating a single owner with each cache line eliminates unnecessary second-level fills, thereby maximizing the effective use of the two-level cache in the chip-multiprocessor.
-
10. A method as in claim 1, wherein the state information in the first tag-state and duplicate of the first tag-state structures includes valid/invalid indication and shared/exclusive indication, wherein a cache line instance found to be invalid cannot be owner, and wherein a cache line instance that is found to be exclusive cannot be involved in a write-back to the second level cache.
-
11. A two-level cache system in a chip-multiprocessor;
- comprising;
means for relaxing the inclusion requirement in the two-level cache system in order to form exclusive two-level caching;
means for providing a first tag-state structure in a first level cache of the two-level cache system, the first tag-state structure having state information;
means for maintaining in a second-level cache of the two-level cache system a duplicate of the first tag-state structure;
means for extending the state information in the duplicate of the first tag-state structure, but not in the first tag-state structure, to include an owner indication;
means for providing in the second-level cache a second tag-state structure so that a simultaneous lookup at the duplicate of the first tag-state structure and the second tag-state structure is possible; and
means for associating a single owner with a cache line at any given time of its lifetime in the chip-multiprocessor. - View Dependent Claims (12, 13, 14)
- comprising;
-
15. A two-level cache system in a chip-multiprocessor, comprising:
-
a plurality of per-processor first level caches, each including an instruction cache and a data cache and each maintaining a first tag-state structure with state information;
an interconnect device;
a second-level cache shared by all the processors, the per-processor first-level caches interfacing with each other and the second cache via the interconnect device, the second-level cache including one or more modules each of which including, storage for a second tag-state structure with its associated state information, a memory controller configured to operatively interface with the processors, a memory, and storage for a duplicate of the first tag-state structures, the state information in the duplicate being extended to include an indication of owner, wherein the two-level cache system is configured so that during a lifetime of a cache line in the chip-multiprocessor only one instance of the cache line, either in the first-level cache or the second-level cache, can be the owner. - View Dependent Claims (16, 17, 18)
-
Specification