Configurable processor system

• US 6,725,364 B1
• Filed: 03/08/2001
• Issued: 04/20/2004
• Est. Priority Date: 03/08/2001
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Crabill, Eric J.
• Primary Examiner(s): Treat, William M.
• Application Number:
  US09/803,524
• Time in Patent Office: 1,139 Days
• Field of Search: 703/26, 703/27, 712/227, 712/248, 712/1, 712/200
• US Class Current: 712/227
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

A programmable integrated circuit can be designed to emulate, on demand, one of several commonly used microprocessors. It contains a configurable instruction processing unit and a superset datapath unit. The instruction processing unit further contains a configurable microcode unit and a non-configurable sequencing unit. The programmable integrated circuit can be programmed so that a microcode compatible with a target microprocessor is installed in the configurable microcode unit. The superset datapath unit is a superset of the datapath elements of all the target microprocessors.

Claims

1. An integrated circuit that can emulate one of a plurality of microprocessors each having registers and executing macroinstructions, said integrated circuit comprising:

a configurable portion storing a microcode;

a non-configurable sequencing logic portion; and

a datapath unit having a register file that is a superset of said registers of said plurality of microprocessors;

wherein said configurable portion, said sequencing logic portion and said datapath unit can execute said macroinstructions to generate compatible results as said one microprocessor.

2. The integrated circuit of claim 1 further comprising a block RAM containing said macroinstructions.

3. The integrated circuit of claim 1 further comprising an on-chip peripheral.

4. The integrated circuit of claim 1 wherein said integrated circuit is a field programmable gate array.

5. The integrated circuit of claim 4 further comprising an on-chip peripheral implemented using configurable logic blocks.