Efficient redundancy calculation system and method for various types of memory devices
First Claim
1. A method for analyzing failures for semiconductor memories comprising the steps of:
- providing a memory device including at least one memory chip, the at least one memory chip including a redundancy calculation region;
testing the at least one memory chip to determine failure addresses of failed components on each memory chip;
inputting the addresses of the failed components to the redundancy calculation region;
comparing the failure addresses to previous failure addresses stored in the redundancy calculation region to determine if new failures have been discovered;
if a match exists between the previous failure addresses and the failure addresses, terminating the failure addresses which match, otherwise storing the failure addresses in the redundancy calculation region;
determining if the at least one memory chip is fixable based on the new failures which have been discovered.
5 Assignments
0 Petitions
Accused Products
Abstract
A method for calculating and analyzing redundancies for semiconductor memories, in accordance with the present invention, includes providing a memory device including at least one memory chip. The at least one memory chip includes a redundancy calculation region. The at least one memory chip is tested to determine failure addresses of failed components on each memory chip. The addresses of the failed components are input to the redundancy calculation region to compare the failure addresses to previous failure addresses stored in the redundancy calculation region to determine if new failures have been discovered. If a match exists between the previous failure addresses and the failure addresses, the failure addresses which match are terminated. Otherwise, the failure addresses are stored in the redundancy calculation region. It is then determined if the at least one memory chip is fixable based on the new failures which have been discovered. A system, preferably for on-chip implementation is also included.
29 Citations
26 Claims
-
1. A method for analyzing failures for semiconductor memories comprising the steps of:
-
providing a memory device including at least one memory chip, the at least one memory chip including a redundancy calculation region;
testing the at least one memory chip to determine failure addresses of failed components on each memory chip;
inputting the addresses of the failed components to the redundancy calculation region;
comparing the failure addresses to previous failure addresses stored in the redundancy calculation region to determine if new failures have been discovered;
if a match exists between the previous failure addresses and the failure addresses, terminating the failure addresses which match, otherwise storing the failure addresses in the redundancy calculation region;
determining if the at least one memory chip is fixable based on the new failures which have been discovered. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A method for analyzing failures for semiconductor memories comprising the steps of:
-
providing a memory device including at least one memory chip, the at least one memory chip including a redundancy calculation region, the redundancy calculation region adapted to receive failure addresses of failed components, the redundancy calculation region further comprising;
comparators for comparing the failure addresses to previous failure addresses to determine if new failures have been discovered, a memory for selectively storing addresses of failures, decision logic for determining if the memory device is fixable based on the new failures which have been discovered;
testing the at least one memory chip to determine failure addresses of failed components on each memory chip;
inputting the addresses of the failed components to the redundancy calculation region;
comparing the failure addresses to previous failure addresses stored in the redundancy calculation region by employing the comparators;
if a match exists between the previous failure addresses and the failure addresses, terminating the failure addresses which match and incrementing a match count, otherwise storing the failure addresses in the redundancy calculation region; and
if the match count meets a threshold value, designating a must repair event to repair the component using redundancies. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
-
-
19. A system for analyzing failures for semiconductor memories comprising:
-
a self testing memory device including at least one memory chip adapted to determine failure addresses of failed components on the at least one memory chip, the at least one memory chip including a redundancy calculation region;
the redundancy calculation region adapted to receive failure addresses of failed components, the redundancy calculation region further comprising;
comparators for comparing the failure addresses to previous failure address to determine if new failures have been discovered, said failure addresses compared by said comparators comprising failure addresses not previously matched to a stored failure address;
a memory for selectively storing address of failures which match previous failure addresses; and
decision logic for determining if the memory device is fixable based on the new failures which have been discovered. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
-
Specification