Built-in self-test for multi-channel transceivers without data alignment

• US 6,725,408 B1
• Filed: 08/07/2000
• Issued: 04/20/2004
• Est. Priority Date: 08/11/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Cao, Jun, Momtaz, Afshin
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Chaudry, Mujtaba
• Application Number:
  US09/632,666
• Time in Patent Office: 1,352 Days
• Field of Search: 714/715, 714/882, 714/739, 714/716, 714/704, 714/742, 714/738, 714/732, 714/729, 714/728, 714/724, 370/249, 375/228
• US Class Current: 714/738
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: H04B 17/19 Self-testing arrangements
• CPC Class Codes: H04B 17/20 of receivers

Abstract

A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplaxy embodiment of the present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern. In order to facilitate the checking process, signature analysis is utilized.

Claims

1. A circuit for testing a transceiver, comprising:

a test pattern generator configured to generate a plurality of test patterns, wherein the plurality of test patterns are associated with a signature;

a multiplexer having a plurality of inputs and an output, each of said plurality of inputs receiving a corresponding test pattern;

a demultiplexer having an input and a plurality of outputs, said input being coupled to said output of said multiplexer; and

a test result evaluation circuit configured to analyze a signal from one of said plurality of outputs of said demultiplexer using said signature to determine whether an error has occurred during transmission of said signal.

2. The circuit according to claim 1, wherein said test patter generator is a linear feedback shift register.

3. The circuit according to claim 1, wherein each of said plurality of test patterns is a pseudo-random bit sequence.

4. The circuit according to claim 1, further comprising:

a clock/data recovery circuit coupled between said multiplexer and demultiplexer and configured to recover data from said output of said multiplexer and relay said recovered data to said input of said demultiplexer.

5. The circuit according to claim 1, wherein said test result evaluation circuit further comprises:

a signature analyzer configured to analyze said signal using said signature;

a compare logic function coupled to said signature analyzer; and

a result recorder configured to record a result of said compare logic function.

6. The circuit according to claim 5, wherein said compare logic function comprises an AND circuit.

7. The circuit according to claim 5, wherein said signature analyzer, further comprises:

a signature recorder controller configured to control when said signal is to be recorded;

a signature recorder configured to record said signal and generate a corresponding signature for said signal, said signature recorder being coupled to and controlled by said signature recorder controller; and

a signature comparator configured to compare said corresponding signature of said signal with said signature associated with said plurality of test patterns.

8. The circuit according to claim 7, wherein said signature recorder is a linear feedback shift register.

9. The circuit according to claim 5, wherein said result recorder is a flip-flop.

10. The circuit according to claim 1, wherein said circuit and said transceiver are integrated into an integrated circuit.

11. The circuit of claim 1, wherein said test evaluation circuit is further configured to analyze two or more signals from two or more of said plurality of outputs of said demultiplexer respectively using said signature to determine whether one or more errors have occurred during transmission of said two or more signals.

12. The circuit of claim 1, wherein said test evaluation circuit is capable of using said signature to identify an error that has occurred in any of said plurality of outputs of said demultiplexer.

13. A circuit for testing a transceiver having a multiplexer and a de-multiplexer, said circuit comprising:

a test pattern generator configured to generate a plurality of test patterns and coupled to a plurality of inputs of said multiplexer, wherein each of the plurality of inputs receives a corresponding test pattern, and wherein the plurality of test patterns is associated with a signature, and

a test result evaluation circuit configured to analyze a signal from one of a plurality of outputs of said de-multiplexer using said signature to determine whether an error has occurred during transmission of said signal;

wherein an output of said multiplexer is coupled to an input of said demultiplexer.

14. The circuit according to claim 13, wherein said circuit is incorporated with said transceiver.

15. The circuit according to claim 13, wherein said test pattern generator is a linear feedback shift register.

16. The circuit according to claim 13, wherein said test result evaluation circuit further comprises:

a signature recorder controller configured to control recording of said signal;

a signature recorder configured to record said signal and generate a corresponding signature based on said signal, said signature recorder being coupled to and controlled by said signature recorder controller; and

a signature comparator configured to analyze said corresponding signature associated with said plurality of test patterns.

17. The circuit according to claim 16, wherein said signature recorder is a linear feedback shift register.

18. The circuit of claim 13, wherein said test evaluation circuit is further configured to analyze two or more signals from two or more of said plurality of outputs of said demultiplexer respectively using said signature to determine whether one or more errors have occurred during transmission of said two or more signals.

19. The circuit of claim 13, wherein said test evaluation circuit is capable of using said signature to identify an error that has occurred in any one of said plurality of outputs of said de-multiplexer.

20. A built-in self-testing circuit for testing an integrated circuit having a transceiver, comprising:

a test pattern generator configured to generate a plurality of test patterns, said plurality of test patterns being associated with a signature;

a multiplexer having a plurality of inputs and an output, said test pattern generator being coupled to said plurality of inputs, each of said plurality of inputs receiving a corresponding test pattern;

a demultiplexer having an input and a plurality of outputs, said input of said demultiplexer being coupled to said output of said multiplexer; and

a test result evaluation circuit configured to receive said plurality of outputs of said demultiplexer and identify one or more of said plurality of outputs of said demultiplexer as having one or more errors using said signature.

21. The circuit according to claim 20, wherein said test pattern generator is a linear feedback shift register having parallel outputs.

22. The circuit according to claim 21, wherein said parallel outputs are respectively coupled to said plurality of inputs of said multiplexer.

23. The circuit according to claim 20, wherein said plurality of test patterns are fed respectively into each of said plurality of inputs of said multiplexer.

24. The circuit according to claim 20, wherein said test result evaluation circuit further comprises:

a signature analyzer configured to analyze signals emanating from said plurality of outputs of said demultiplexer;

an AND logic function coupled to said signature analyzer to determine whether any of corresponding signatures of said signals does not match said signature associated with said plurality of test patterns; and

a result recorder configured to record a result of said AND logic function.

25. The circuit according to claim 24, wherein said signature analyzer further comprises:

a signature recorder controller configured to control recording of each of said signals;

a signature recorder configured to record each of said signals and generate a corresponding signature based on each of said signals, said signature recorder being coupled to and controlled by said signature recorder controller; and

a signature comparator configured to compare each of said corresponding signatures of said signals with said signature associated within said plurality of test patterns.

26. The circuit according to claim 25, wherein said signature recorder is a linear feedback shift register.

27. The circuit according to claim 20, wherein said built-in self-testing circuit is integrated with said integrated circuit having a transceiver.

28. A method for testing an integrated circuit having a transceiver, said transceiver having a multiplexer coupled to a demultiplexer, said method comprising:

generating a plurality of test patterns, the plurality of test patterns being associated with a test signature;

receiving at each of the plurality of inputs of said multiplexer, a corresponding test pattern; and

evaluating each of a plurality of outputs of said demultiplexer using said test signature to identify any error.

29. The method according to claim 28, wherein said steps are performed by circuitry within said integrated circuit having a transceiver.

30. The method according to claim 28, wherein said evaluating step further comprises:

recording an appropriate signal from each of said plurality of outputs of said demultiplexer;

identifying a corresponding signature for each of said appropriate signals; and

comparing each of said corresponding signatures to said test signature.