Timing closure methodology

• US 6,725,438 B2
• Filed: 04/24/2002
• Issued: 04/20/2004
• Est. Priority Date: 12/24/1997
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Magma Design Automation (Synopsys Incorporated)
• Inventors: van Ginneken, Lukas P. P. P.
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US10/134,076
• Publication Number:
  US 20020116685A1
• Time in Patent Office: 727 Days
• Field of Search: 716/2, 716/7-14
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/27 using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

Claims

1. An automated method for designing an initial integrated circuit layout with a computer, based upon an electronic circuit description and by using a cell library containing cells that each have an associated relative delay value, comprising the steps of:

(a) selecting a plurality of cells from the cell library that are intended to be coupled to each other with a plurality of wires and that can be used to implement a digital circuit based on the electronic circuit description input to the computer; and

(b) determining, using a portion of a computer program that contains a sequence of instructions, an initial intended area of each of the selected plurality of cells, the initial intended area of at least some of the selected plurality of cells being determined using the associated relative delay values of the some selected cells and initial intended lengths of some of the wires coupled to each of said some selected cells in order to meet predetermined timing constraints associated with each of said some cells that are coupled to another cell.

2. The automated method of claim 1 further comprising:

routing the digital circuit to generate the integrated circuit layout using a finalized area of each of the selected plurality of cells and finalized wire lengths of the wires coupled to each of the selected plurality of cells.

3. The automated method of claim 2 further comprising:

prior to the step of routing, finalizing the area of each of the selected plurality of cells and the wire lengths of the wires coupled to each of the selected plurality of cells.

4. The method of claim 1 wherein the plurality of cells are coupled to each other based on the electronic circuit description input to the computer.

5. The automated method of claim 1 wherein each of the plurality of wires has an associated capacitive load value;

and

wherein each wire is associated with a net weight value that represents a sensitivity of a total area of the digital circuit of step (a) with respect to the associated capacitive load value of the wire.

6. The automated method of claim 5 wherein the net weight w_i of the wire coupled to a selected cell is:

7. The automated method of claim 6 wherein the initial intended areas of said some selected cells are chosen based upon the net weight w_i in order to meet said predetermined timing constraints.

8. The automated method of claim 1 wherein the initial intended areas of said some selected cells are chosen based upon a length of said some wires coupled to said some selected cell.

9. The automated method of claim 6 wherein the initial intended areas of said some selected cells are chosen based upon the net weight w_i of the wires coupled to said some selected cells and lengths of the wires coupled to said some selected cells.

10. The automated method of claim 1 further comprising:

inserting a buffer in one of the plurality of wires of step (a) to reduce an area of a cell coupled to the wire.

11. The automated method of claim 10 wherein the step of inserting the buffer comprises:

determining a wire in the digital circuit of step (a) into which the buffer can be inserted to reduce the area of the cell coupled to the wire by a specific area size; and

inserting the buffer into the wire if the area of the buffer is less than the specific area size, prior to the step (b) of determining the initial intended area of each of the selected plurality of cells.

12. The automated method of claim 1 further comprising:

stretching the associated relative delay value of a selected cell of the plurality of the selected cells to decrease an area of the selected cell.

13. The automated method of claim 1 further comprising:

stretching the associated relative delay values of the plurality of selected cells to decrease an area of each of the plurality of selected cells.

14. The automated method of claim 1 further comprising:

compressing the associated relative delay value of a selected cell of the plurality of the selected cells to assist in satisfying the predetermined timing constraints.

15. The automated method of claim 14 wherein the compressing step is limited by a gain requirement of the selected cell.

16. The automated method of claim 1 further comprising:

compressing the associated relative delay values of the plurality of the selected cells to assist in satisfying the predetermined timing constraints.

17. The automated method of claim 1 wherein a group of said some cells are assigned in buckets and operated upon in order to determined the initial intended area of each of the group of said some cells.

18. The automated method of claim 17 wherein the group of said some cells ranges from 20 to 200 cells.

19. An integrated circuit layout produced in accordance with the automated method of claim 1.