Method and apparatus for defining and modifying connections between logic cores implemented on programmable logic devices

• US 6,725,441 B1
• Filed: 03/22/2000
• Issued: 04/20/2004
• Est. Priority Date: 03/22/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Keller, Eric R., Patterson, Cameron D.
• Primary Examiner(s): Von Buhr, Maria N.
• Application Number:
  US09/533,092
• Time in Patent Office: 1,490 Days
• Field of Search: 700/18, 716/1, 716/12-18, 713/100, 326/37-41, 326/74, 712/10-17
• US Class Current: 716/117
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method and apparatus for generating a configuration bitstream for a programmable logic device using logic ports associated with logic cores. Logic ports are associated with respective ones of a plurality of logic cores, and logical connections are made between selected ones of the ports of the logic cores. Source pins, wherein a pin represents an output resource of a programmable element of the programmable logic device, are associated with selected ones of the ports. A sink pin represents an input resource of a programmable element of the programmable logic device, and sink pins are associated with selected ones of the ports. In response to a route programming interface call that references a source port and a sink port, bits for the configuration bitstream are generated for routing resources to connect selected ones of the source pins to selected ones of the sink pins. Usage of logic ports assists in runtime reconfiguration of logic.

Claims

1. A computer-implemented method for generating a configuration bitstream for a programmable logic device, comprising:

associating logic ports with respective ones of a plurality of logic cores;

establishing logical connections between selected ones of the ports;

associating source pins with selected ones of the ports, wherein a pin represents an output resource of a configurable element of the programmable logic device;

associating sink pins with selected ones of the ports, wherein a sink pin represents an input resource of a configurable element of the programmable logic device; and

generating bits in the configuration bitstream for configuration of routing resources to connect selected ones of the source pins to selected ones of the sink pins responsive to programming interface calls calling for connection of referenced ports.

2. The method of claim 1, wherein the ports are of types input and output, and at least one of the logical connections between selected ones of the ports is from a first input port to a second input port.

3. The method of claim 1, wherein the ports are of types input and output, and at least one of the logical connections between selected ones of the ports is from an input port to an output port.

4. The method of claim 1, wherein the ports are of types input and output, and at least one of the logical connections between selected ones of the ports is from an output port to an input port.

5. The method of claim 1, wherein the ports are of types input and output, and at least one of the logical connections between selected ones of the ports is from a first output port to a second output port.

6. The method of claim 1, wherein the ports are of types input and output, at least one of the logical connections between selected ones of the ports is from a first input port to a second input port, at least one of the logical connections is from an input port to an output port, at least one of the logical connections is from an output port to an input port, and at least one of the logical connections is from a first output port to a second output port.

7. The method of claim 1, further comprising in response to a programming interface call calling for connection of referenced source and sink ports:

identifying a pin that drives the source port;

identifying one or more pins driven by the sink port; and

generating bits for the configuration bitstream to connect the pin that drives the source port to the one or more pins driven by the sink port.

8. The method of claim 7, further comprising generating bits in the configuration bitstream for configuration of routing resources to disconnect one of the source pins from one or more sink pins responsive to an unroute programming interface call that references a port.

9. The method of claim 8, further comprising:

saving data indicating which pins drive which ports;

saving data indicating which sets of one or more pins are driven by which ports, respectively; and

deleting data indicating a set of one or more pins that are driven by the port referenced in the unroute programming interface call.

10. The method of claim 1, further comprising defining the logic cores and ports with object-oriented classes.

11. The method of claim 10, wherein the object-oriented classes are Java classes.

12. A computer-implemented method for generating a configuration bitstream for a programmable logic device, comprising:

associating a logical output port with a first logic core;

associating a logical input port with a second logic core;

responsive to a first programming interface call, instantiating the first logic core in the configuration bitstream and associating the logical output port with a pin within the first logic core;

responsive to a second programming interface call, instantiating the second logic core in the configuration bitstream and associating the logical input port with one or more pins within the second logic core; and

generating bits in the configuration bitstream for configuration of routing resources to connect the pin within the first logic core to the one or more pins within the second logic core responsive to a third programming interface call calling for routing and referencing the input and output ports.

13. The method of claim 12, wherein the third programming interface call has as input parameters a source and a sink, the source having as possible types an output port and a pin, and the sink having as possible types an input port and a pin.

14. The method of claim 13, further comprising in response to the third programming interface call:

if the source is a port, saving data indicating that the source drives the sink;

if the sink is a port, saving data indicating that the sink is driven by the source.

15. The method of claim 14, further comprising in response to an unroute programming interface call having as an input parameter a port, clearing selected bits in the configuration bitstream to disconnect pins associated with the port.

16. The method of claim 15, further comprising in response to the unroute programming interface call:

identifying one or more pins driven by the port;

identifying a pin that drives the port;

generating bits in the configuration bitstream to disconnect the one or more pins driven by the port from the pin that drives the port; and

deleting data indicating pins and ports driven by the port.

17. The method of claim 15, further comprising in response to a reverse-unroute programming interface call having as an input parameter a port:

identifying one or more pins driven by the port;

identifying a pin that drives the port;

generating bits in the configuration bitstream to disconnect the one or more pins driven by the port from the pin that drives the port; and

deleting data indicating the pin that drives the port.

18. A computer-implemented method for generating a configuration bitstream for a programmable logic device, comprising:

associating a logical output port with a first logic core;

associating a;

logical input port with a second logic core;

associating the logical output port of the first logic core with the logical input port of the second logic core;

responsive to a first programming interface call, instantiating the first logic core in a configuration bitstream and associating the logical output port with a pin within the first logic core; and

responsive to a second programming interface call, instantiating the second logic core in the configuration bitstream, associating the logical input port with the one or more pins within the second logic core, and generating configuration bits for configuration of routing resources to connect the pin within the first logic core to the one or more pins within the second logic core.

19. A computer-implemented method for generating a configuration bitstream for a programmable logic device, comprising:

associating a plurality of logical output ports with a first logic core;

associating a plurality of logical input ports with a second logic core;

responsive to a first programming interface call, instantiating the first logic core in the configuration bitstream and associating the logical output ports with pins within the first logic core;

responsive to a second programming interface call, instantiating the second logic core in the configuration bitstream and associating the logical input ports with pins within the second logic core; and

generating bits in the configuration bitstream for configuration of routing resources to connect the pins within the first logic core to pins within the second logic core responsive to a third programming interface call referencing the first and second pluralities of input and output ports.

20. An apparatus for generating a configuration bitstream for a programmable logic device, comprising:

means for associating logic ports with respective ones of a plurality of logic cores;

means for establishing logical connections between selected ones of the ports;

means for associating source pins with selected ones of the ports, wherein a pin represents an output resource of a configurable element of the programmable logic device;

means for associating sink pins with selected ones of the ports, wherein a sink pin represents an input resource of a configurable element of the programmable logic device; and

means for generating bits in the configuration bitstream for configuration of routing resources to connect selected ones of the source pins to selected ones of the sink pins responsive to programming interface calls calling for connection of referenced ports.