DRAM having offset vertical transistors and method

• US 6,727,141 B1
• Filed: 01/14/2003
• Issued: 04/27/2004
• Est. Priority Date: 01/14/2003
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bronner, Gary B., Kim, Byeong, Divakaruni, Ramachandra, Mandelman, Jack A.
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Le, Thao X.
• Application Number:
  US10/342,419
• Time in Patent Office: 469 Days
• Field of Search: 438/239, 438/240, 438/241, 438/242, 438/243, 438/244, 438/386, 438/387, 438/270, 438/268, 257/301, 257/302
• US Class Current: 438/242
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

The distance between buried straps in a DRAM array of trench capacitor/vertical transistor cells is increased by offsetting adjacent cells by a vertical offset distance, so that the total distance between adjacent straps is increased without increasing the horizontal distance between cells.

Claims

1. A method of making a DRAM array having cells containing trench capacitors and vertical access transistors comprising the steps of:

preparing a semiconductor substrate;

forming a set of trenches in said substrate;

forming a set of capacitors within said set of trenches, members of said set of capacitors having an interior electrode with a top surface;

recessing a first subset of said interior electrodes in a first subset of cells with a top surface to a first depth;

recessing a second subset of said interior electrodes in a second subset of cells with a top surface to a second depth greater than said first depth by an offset amount, individual members of said second subset being located

adjacent to individual members of said first subset;

forming vertical transistors in each of said first subset and said second subset, whereby the distance between adjacent top surfaces in adjacent ones of said first and second subsets is increased by an amount dependent on said offset amount; and

connecting said first and second subsets of cells to form said DRAM array.

2. A method according to claim 1, in which said vertical transistors in said first and second subsets are formed simultaneously at vertical locations differing by said offset amount, whereby transistors in said first and second subsets of cells have substantially the same vertical extent at different vertical positions;

cells in said first and second subsets are filled with gate conductive material simultaneously;

a second recess is performed only on gate conductive material in said second subset, whereby a top surface of said vertical transistors in said second subset is lower by said offset distance than a corresponding top surface of said vertical transistors in said first subset;

self-aligned junctions are formed simultaneously in said first and second subsets of cells above said vertical transistors, whereby cells in said second subset have junctions with a greater height than corresponding junctions in said first subset.

3. A method according to claim 2, in which said self-aligned junctions are formed in said semiconductor substrate above said vertical transistors by gas phase doping.

4. A method according to claim 2, in which a buried strap and trench top insulator are formed simultaneously in said first and second subsets simultaneously, whereby said first and second subsets have a top surface of said trench top insulator at vertical positions differing by said offset distance.

5. A method according to claim 3, in which a buried strap and trench top insulator are formed simultaneously in said first and second subsets simultaneously, whereby said first and second subsets have a top surface of said trench top insulator at vertical positions differing by said offset distance.

6. A method according to claim 2, in which said self-aligned junctions in both said first and second subsets extend from a top edge of said vertical transistors to a surface of said substrate.

7. A method according to claim 3, in which said self-aligned junctions in both said first and second subsets extend from a top edge of said vertical transistors to a surface of said substrate.

8. A method according to claim 4, in which said self-aligned junctions in both said first and second subsets extend from a top edge of said vertical transistors to a surface of said substrate.

9. A method according to claim 5, in which said self-aligned junctions in both said first and second subsets extend from a top edge of said vertical transistors to a surface of said substrate.

10. A method according to claim 1, in which a first recess step is performed in both said subsets;

a second recess step is performed only on said second subset, whereby said center electrodes in said second subset are recessed below corresponding top surfaces in said first subset by said offset distance;

a gas phase doping step, a buried strap formation step and a trench top insulator step are performed on both subsets above said center electrodes, whereby both subsets have buried straps and insulators, those in said second subset being greater in vertical extent by said offset distance than those in said first subset;

gate insulators and gate electrodes are formed simultaneously in said first and second subsets at the same vertical position, whereby transistors in said first and second subsets of cells are located at substantially the same height.

11. A method according to claim 10, in which nitride sidewalls are formed on the trench walls after the center electrodes of both subsets have been recessed;

a wet etch removes the trench oxide collar in the area between the recessed center electrodes and the bottom of the nitride sidewalls;

a gas phase doping step forms extended transistor electrodes in the substrate below the nitride sidewalls;

a buried strap is formed to connect the center electrodes with the extended transistor electrodes; and

a trench top insulator isolates the buried strap from the upper portion of the trench.

12. A method according to claim 11, in which a thermal oxide is grown on the exposed trench walls below the nitride sidewalls before the nitride sidewalls are stripped, whereby the extended transistor electrodes are insulated from the gate electrode;

and

the nitride sidewalls in both subsets are stripped and gate insulators and gate conductors are formed, whereby said second subset has extended lower transistor electrodes greater by said offset distance than said first subset and said first and second subsets have vertical transistors at substantially the same height.