Methods for fabricating inductor for integrated circuit or integrated circuit package

• US 6,727,154 B2
• Filed: 09/10/2002
• Issued: 04/27/2004
• Est. Priority Date: 11/23/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gardner, Donald S.
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US10/238,539
• Publication Number:
  US 20030006474A1
• Time in Patent Office: 595 Days
• Field of Search: 438/328, 438/381, 438/378, 257/528, 257/531-533
• US Class Current: 438/329
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0046 with a conductive path having a bridge
• CPC Class Codes: H01F 41/042 by thin film techniques
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

An inductor for an integrated circuit or integrated circuit package comprises a three-dimensional structure. In one embodiment the inductor is arranged on an integrated circuit substrate in at least two rows, each row comprising upper segments and lower segments, with the upper segments being longer than the lower segments. The upper segments in a first row are offset 180 degrees from those in an adjoining row to provide greater coupling of magnetic flux. The materials and geometry are optimized to provide a low resistance inductor for use in high performance integrated circuits. In another embodiment the inductor is arranged on an integrated circuit package substrate. Also described are methods of fabricating the inductor on an integrated circuit or as part of an integrated circuit package.

Claims

1. A method comprising:

forming a first dielectric layer in a manner that varies in the Z-dimension; and

forming a first conductive layer over the first dielectric layer, the first conductive layer also varying in the Z-dimension, the first conductive layer having a length and a width, the length being substantially greater than the width, the first conductive layer being arranged in a substantially straight line along the X-dimension, and the first conductive layer comprising upper segments and lower segments, the upper segments being longer than the lower segments.

2. The method recited in claim 1 wherein, in forming the first dielectric layer, the first dielectric layer is arranged in a stepped manner.

3. The method recited in claim 1 wherein, in forming the first dielectric layer, the first dielectric layer is arranged in an undulating manner.

4. The method recited in claim 1 wherein, in forming the first dielectric layer, the first dielectric layer is arranged in a manner that alternates between trenches and pedestals.

5. A method as recited in claim 1 and further comprising:

forming a second dielectric layer in a manner that varies in the Z-dimension;

forming a second conductive layer over the second dielectric layer, the second conductive layer also varying in the Z-dimension, the second conductive layer having a length and a width, the length being substantially greater than the width, the second conductive layer being arranged in a substantially straight line along the X-dimension, and the second conductive layer comprising upper segments and lower segments, the upper segments being longer than the lower segments; and

coupling the second conductive layer to the first conductive layer.

6. The method recited in claim 5 wherein, in forming the second conductive layer, the upper segments in the first conductive layer are offset 180 degrees from the upper segments in the second conductive layer.

7. The method recited in claim 1 wherein, in forming the first conductive layer, the first conductive layer comprises material from the group consisting of copper, aluminum, tungsten, molybdenum, titanium, gold, silver, palladium, a metal silicide, doped polysilicon, or is an alloy whose constituents are from the group.

8. The method recited in claim 1 wherein, in forming the first conductive layer, the first conductive layer comprises magnetic material.

9. The method recited in claim 8 wherein, in forming the first conductive layer, the magnetic material is from the group consisting of nickel-iron, cobalt-zirconium-tantalum, iron-tantalum-nickel, nickel-iron-rhenium, and ferro-silicon.

10. The method recited in claim 8 wherein, in forming the first conductive layer, the magnetic material is from the group consisting of iron, nickel, cobalt, manganese, zinc, zirconium, tantalum, rhenium, silicon, and the rare earth elements, or is an alloy whose constituents are from the group.

11. A method comprising:

forming at least one multi-level inductive element on a substrate in a serpentine pattern comprising at least two rows, wherein each row comprises upper conductive segments and lower conductive segments, and in at least one row the upper conductive segments are longer than the lower conductive segments; and

mounting an integrated circuit on the substrate.

12. The method recited in claim 11 wherein, in forming, the upper conductive segments and the lower conductive segments are arranged in a stepped manner.

13. The method recited in claim 11 wherein, in forming, the upper conductive segments and the lower conductive segments are arranged in an undulating manner.

14. The method recited in claim 11 wherein, in forming, the upper conductive segments in one row are offset 180 degrees from the upper conductive segments in an adjacent row.

15. The method recited in claim 11 wherein, in forming, the at least one multi-level inductive element comprises at least one layer of magnetic material.

16. A method comprising:

forming at least one multi-level inductive element on a substrate in a serpentine pattern comprising at least two rows, wherein each row comprises upper conductive segments and lower conductive segments, and in at least one row the upper conductive segments are longer than the lower conductive segments.

17. The method recited in claim 16 wherein, in forming, the upper conductive segments and the lower conductive segments are arranged in a stepped manner.

18. The method recited in claim 16 wherein, in forming, the upper conductive segments and the lower conductive segments are arranged in an undulating manner.

19. The method recited in claim 16 wherein, in forming, the upper conductive segments in one row are offset 180 degrees from the upper conductive segments in an adjacent row.

20. The method recited in claim 16 wherein, in forming, the at least one multi-level inductive element comprises at least one layer of magnetic material.