Semiconductor capacitively-coupled NDR device and related applications in high-density high-speed memories and in power switches

• US 6,727,529 B2
• Filed: 03/20/2002
• Issued: 04/27/2004
• Est. Priority Date: 06/05/1998
• Status: Expired due to Fees

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford Management Co.)
• Inventors: Nemati, Farid, Plummer, James D.
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US10/103,241
• Publication Number:
  US 20020096689A1
• Time in Patent Office: 769 Days
• Field of Search: 257/133, 257/147, 257/155, 365/180
• US Class Current: 257/133
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1027 Thyristors
• CPC Class Codes: H01L 29/41716 Cathode or anode electrodes for thyristors
• CPC Class Codes: H01L 29/42308 Gate electrodes for thyristors
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components

Abstract

A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F² footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.

Claims

1. A semiconductor device having a thyristor device with NDR characteristics, the device comprising:

at least two contiguous regions of the thyristor device, said at least two contiguous regions being of opposite polarity; and

control means, located adjacent to and facing said at least one of the regions of the thyristor device, for capacitively coupling at least part of a voltage pulse to said at least one of the regions of the thyristor device, the thyristor device including the control means and said at least two contiguous regions,

with said at least two contiguous regions, the control means for preponderantly controlling switching of the thyristor device from a current-passing mode to a current-blocking mode in response to the control means coupling at least one edge of a first voltage pulse to said at least one of the regions, and from a current-blocking mode to a current-passing mode in response to the control means coupling at least one edge of a second voltage pulse to said at least one of the regions, each of the first and second voltage pulses having a common polarity.

2. A semiconductor device, according to claim 1, further including at least one other thyristor device that also has at least two contiguous regions of opposite polarity and a control means, located adjacent to and facing at least one of the regions of the one other thyristor device, for capacitively coupling an edge of a voltage pulse to said at least one of the regions of the one other thyristor device.

3. A semiconductor device, according to claim 1, further including a layer of insulative material as part of a silicon-on-insulator structure, wherein the thyristor device is located adjacent the insulative material.

4. A semiconductor device, comprising:

memory means for providing a plurality of accessible and addressable memory cells, each of the memory cells having an NDR-type thyristor means including a multi-regioned body and control means for capacitively coupling at least part of a voltage pulse to at least part of the multi-regioned body; and

with the multi-regioned body, the control means for switching of the thyristor means from a current-passing mode to a current-blocking mode in response to the control means coupling at least one edge of a first voltage pulse to said at least part of the multi-regioned body, and from a current-blocking mode to a current-passing mode in response to the control means coupling at least one edge of a second voltage pulse to said at least part of the multi-regioned body, each of the first and second voltage pulses having a common polarity.

5. A semiconductor device, according to claim 4, wherein each of memory cells includes a storage means for storing a data bit and includes a controllable access means for providing access to the storage means, and wherein the control means of the thyristor device is for enhancing writing access to the storage means.

6. A semiconductor device, comprising:

memory means for providing an accessible and addressable memory cell having an NDR-type thyristor means including a multi-regioned body and control means for capacitively coupling at least part of a voltage pulse to at least part of the multi-regioned body; and

with the multi-regioned body, the control means for switching of the thyristor means from a current-passing mode to a current-blocking mode in response to the control means coupling at least one edge of a first voltage pulse to said at least part of the multi-regioned body, and from a current-blocking made to a current-passing mode in response to the control means coupling at least one edge of a second voltage pulse to said at least part of the multi-regioned body, each of the first and second voltage pulses having a common polarity.

7. A semiconductor device, according to claim 6, wherein the control means is responsive to a word line and the thyristor device provides two stable states for the memory cell.

8. A semiconductor device, according to claim 6, wherein at least two regions of the multi-regioned body are vertically arranged.

9. A semiconductor device, according to claim 6, wherein the control means and the multi-regioned body for providing switching of the thyristor device between a current-passing mode and a current-blocking mode independent of any insulated-gate field-effect transistor inversion channel formation against said at least one of the regions.

10. A semiconductor device, according to claim 9, wherein said memory means is an SRAM device.

11. A semiconductor device, according to claim 6, wherein said memory cell is an SRAM cell.

12. A semiconductor device, according to claim 11, wherein the SRAM cell includes a storage node, a bit line, a first word line, a second word line, an access circuit having means connected to the first word line for providing read and write access between the storage node and the bit line.

13. A semiconductor memory device, according to claim 6, further comprising means for maintaining the thyristor device in one of two stable states after the thyristor device switches between current-passing and current-blocking modes.

14. A semiconductor device having a thyristor device with NDR characteristics, the semiconductor device comprising:

at least two contiguous regions of the thyristor device, said at least two contiguous regions being of opposite polarity;

control means, located adjacent to and facing said at least one of the regions of the thyristor device, for capacitively coupling at least part of a voltage pulse to said at least one of the regions of the thyristor device, the thyristor device including the control means and said at least two contiguous regions, and

with said at least two contiguous regions, the control means for switching the thyristor device from a current-passing mode to a current-blocking mode in response to the control means coupling at least part of a first voltage pulse to said at least one of the regions, and from a current-blocking mode to a current-passing mode in response to the control means coupling at least part of a second voltage pulse to said at least one of the regions, each of the first and second voltage pulses having a common polarity, the control means, the switching being independent of any insulated-gate field-effect transistor inversion channel formation against said at least one of the regions.

15. A semiconductor memory device, according to claim 14, wherein the control means and said at least two contiguous regions provide at least preponderant control for switching of the thyristor device between a current-passing mode and a current-blocking mode in response to the control means coupling at least part of a voltage pulse to said at least one of the regions.