Electrically programmed MOS transistor source/drain series resistance

• US 6,727,534 B1
• Filed: 12/20/2001
• Issued: 04/27/2004
• Est. Priority Date: 12/20/2001
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Buller, James F., Xiang, Qi, Wristers, Derick J.
• Primary Examiner(s): Zaribian, Amir
• Assistant Examiner(s): Soward, Ida M.
• Application Number:
  US10/022,847
• Time in Patent Office: 859 Days
• Field of Search: 257/336, 257/344, 257/408, 257/288
• US Class Current: 257/288
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

High-speed MOS transistors are provided by forming a conductive layer embedded in transistor gate sidewall spacers. The embedded conductive layer is electrically insulated from the gate electrode and the source/drain regions of the transistor. The embedded conductive layer is positioned over the source/drain extensions and causes charge to accumulate in the source/drain extensions lowering the series resistance of the source/drain regions.

Claims

1. A semiconductor device comprising:

a semiconductor substrate with a transistor formed thereon, the transistor comprising a gate electrode with opposing sidewalls formed on said substrate;

an active region formed in said substrate;

insulating sidewall spacers formed alongside and in contact with the gate electrode opposing sidewalls; and

a conductive layer embedded in said sidewall spacers, said conductive layer being electrically insulated from said gate electrode and said active region,

wherein the embedded conductive layer comprises a conductive material selected from the group consisting of a metal and a metal silicide.

2. The semiconductor device of claim 1, wherein said active region comprises source and drain regions.

3. The semiconductor device of claim 1, further comprising a gate insulating layer interposed between said gate electrode and said active region.

4. The semiconductor device of claim 1, wherein said sidewall spacer comprises silicon nitride.

5. The semiconductor device of claim 1, wherein the embedded conductive layer has a thickness of about 50 Å

to about 300 Å

.

6. The semiconductor device of claim 1, wherein the sidewall spacers have a width of about 300 Å

to about 2000 Å

.

7. The semiconductor device of claim 1, wherein the embedded conductive layer has a width of about 100 Å

to about 1800 Å

.

8. The semiconductor device of claim 1, wherein the conductive layer is spaced apart from the a gate electrode sidewall by a distance of about 50 Å

to about 500 Å

.

9. The semiconductor device of claim 1, wherein said embedded conductive layer is biased.

10. The semiconductor device of claim 1, wherein said embedded conductive layer is floating.

11. A semiconductor device comprising:

a semiconductor substrate with a transistor formed thereon, the transistor comprising a gate electrode with opposing sidewalls formed on said substrate;

an active region formed in said substrate;

insulating sidewall spacers formed alongside and in contact with the gate electrode opposing sidewalls; and

a conductive layer embedded in said sidewall spacers, said conductive layer being electrically insulated from said gate electrode and said active region,

wherein the embedded conductive layer comprises a conductive polysilicon.