Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling

• US 6,727,545 B2
• Filed: 07/26/2001
• Issued: 04/27/2004
• Est. Priority Date: 09/20/2000
• Status: Expired due to Term

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Wang, Chih Hsin, Levi, Amitay
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US09/916,555
• Publication Number:
  US 20020034849A1
• Time in Patent Office: 1,006 Days
• Field of Search: 257/314-326
• US Class Current: 257/321
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction, and an apparatus formed thereby. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that include indentations or different widths. The trenches are filled with a conducting material to form blocks of the conducting material that constitute source regions with a first portion that is disposed adjacent to but insulated from the floating gate, and a second portion that this disposed over but insulated from the floating gate.

Claims

1. An electrically programmable and erasable memory device comprising:

a substrate of semiconductor material of a first conductivity type;

first and second spaced-apart regions of a second conductivity type formed in the substrate, with a channel region therebetween;

an electrically conductive floating gate disposed vertically over and insulated from a portion of said channel region and a portion of the first region;

an electrically conductive source region electrically connected to the first region in the substrate, the source region having a lower portion that is disposed vertically over the first region and laterally adjacent to and insulated from the floating gate, and an upper portion that extends up and over the floating gate and terminates in a first end that is disposed vertically over and insulated from the floating gate;

an electrically conductive control gate having a first portion and a second portion, the first control gate portion being disposed laterally adjacent to and insulated from the floating gate, and the second control gate portion extends up and over the floating gate and terminates in a second end that is disposed vertically over and insulated from the floating gate;

wherein the first and second ends are disposed laterally adjacent to and insulated from each other such that no portion of the control gate is disposed directly between the floating gate and the source region; and

insulation material disposed directly between the first end and the floating gate, and having a thickness for permitting voltage coupling therebetween.

2. An array of electrically programmable and erasable memory devices comprising:

a substrate of semiconductor material of a first conductivity type;

spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions; and

each of the active regions including a column of pairs of memory cells extending in the first direction, each of the memory cell pairs including;

a first region and a pair of second regions spaced apart in the substrate and having a second conductivity type, with channel regions formed in the substrate between the first region and the second regions,

a pair of electrically conductive floating gates each disposed vertically over and insulated from a portion of one of the channel regions and a portion of the first region,

an electrically conductive source region electrically connected to the first region in the substrate, the source region having a lower portion that is disposed vertically over the first region and laterally adjacent to and insulated from the pair of floating gates, and an upper portion that extends up and over the floating gates and terminates in a pair of first ends that each is disposed vertically over and insulated from one of the floating gates,

a pair of electrically conductive control gates each having a first portion and a second portion, wherein for each of the control gates, the first control gate portion is disposed laterally adjacent to and insulated from one of the floating gates and the second control gate portion extends up and over the one floating gate and terminates in a second end that is disposed vertically over and insulated from the one floating gate,

wherein each of the first ends is disposed laterally adjacent to and insulated from one of the second ends such that no portion of the control gates is disposed directly between the floating gates and the source region, and

insulation material disposed directly between the first ends and the floating gates, and having a thickness for permitting voltage coupling therebetween.

3. An electrically programmable and erasable memory device comprising:

a substrate of semiconductor material of a first conductivity type;

first and second spaced-apart regions of a second conductivity type formed in the substrate, with a channel region therebetween;

an electrically conductive floating gate disposed vertically over and insulated from a portion of said channel region and a portion of the first region;

an electrically conductive source region electrically connected to the first region in the substrate, the source region having a lower portion that is disposed vertically over the first region and laterally adjacent to and insulated from the floating gate, and an upper portion that extends up and over the floating gate and terminates in a first end that is disposed vertically over and insulated from the floating gate;

an electrically conductive control gate having a first portion and a second portion, the first control gate portion being disposed laterally adjacent to and insulated from the floating gate, and the second control gate portion extends up and over the floating gate and terminates in a second end that is disposed vertically over and insulated from the floating gate;

wherein the first and second ends are disposed laterally adjacent to and insulated from each other such that there is no vertical overlap between the control gate and the source region;

insulation material disposed directly between the source region lower portion and the floating gate, and having a thickness permitting voltage coupling therethrough; and

insulation material disposed directly between the first end and the floating gate, and having a thickness permitting voltage coupling therethrough.

4. The device of claim 3, further comprising:

insulation material disposed directly between the floating gate and the second end, and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough.

5. An array of electrically programmable and erasable memory devices comprising:

a substrate of semiconductor material of a first conductivity type;

spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions; and

each of the active regions including a column of pairs of memory cells extending in the first direction, each of the memory cell pairs including;

a first region and a pair of second regions spaced apart in the substrate and having a second conductivity type, with channel regions formed in the substrate between the first region and the second regions,

a pair of electrically conductive floating gates each disposed vertically over and insulated from a portion of one of the channel regions and a portion of the first region,

an electrically conductive source region electrically connected to the first region in the substrate, the source region having a lower portion that is disposed vertically over the first region and laterally adjacent to and insulated from the pair of floating gates, and an upper portion that extends up and over the floating gates and terminates in a pair of first ends that each is disposed vertically over and insulated from one of the floating gates,

a pair of electrically conductive control gates each having a first portion and a second portion, wherein for each of the control gates, the first control gate portion is disposed laterally adjacent to and insulated from one of the floating gates and the second control gate portion extends up and over the one floating gate and terminates in a second end that is disposed vertically over and insulated from the one floating gate, and wherein each of the first ends is disposed laterally adjacent to and insulated from one of the second ends such that there is no vertical overlap between the control gates and the source region,

insulation material disposed directly between the source region lower portion and the pair of floating gates, and having a thickness permitting voltage coupling therethrough, and

insulation material disposed directly between the the first ends and the floating gates, and having a thickness permitting voltage coupling therethrough.

6. The device of claim 5, wherein each of the source regions extends across the active regions and isolation regions in a second direction substantially perpendicular to the first direction and intercepts one of the memory cell pairs in each of the active regions.

7. The device of claim 5, wherein each of the memory cell pairs further comprises:

insulation material disposed directly between the floating gates and the second ends, and having a thickness permitting Fowler-Nordheim tunneling of charges therethrough.