Integrated inductive circuits

• US 6,727,570 B2
• Filed: 02/21/2002
• Issued: 04/27/2004
• Est. Priority Date: 02/21/2002
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Woo, Chong
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/081,089
• Publication Number:
  US 20030155630A1
• Time in Patent Office: 796 Days
• Field of Search: 257/3, 257/4, 257/528, 257/531, 600/347
• US Class Current: 257/531
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors

Abstract

An integrated inductor may be formed over a substrate. An aperture may be formed by a backside etch through the semiconductor substrate underneath the integrated inductor. The aperture may then be filled with a dielectric material. As a result of the removal of the underlying substrate material, magnetic and capacitive coupling of the inductor to the substrate may be reduced. In addition, in some cases, the presence of the dielectric may facilitate attachment of the resulting die to a leadframe and package without degrading the inductor'"'"'s performance and may provide better structural support.

Claims

1. An integrated circuit comprising:

a substrate;

an integrated inductor formed over a first side of said substrate;

an aperture formed in said substrate from a second side of said substrate underneath said inductor; and

a dielectric material formed in said aperture such that the material directly underneath said inductor is entirely a dielectric material.

2. The circuit of claim 1 including an intervening layer between said inductor and said substrate.

3. The circuit of claim 2 wherein said intervening layer is a field oxide region.

4. The circuit of claim 2 wherein said aperture is formed completely through said substrate to said intervening layer.

5. The circuit of claim 4 wherein said aperture encompasses the entire region beneath said integrated inductor.

6. An integrated circuit comprising:

a substrate;

an inductor formed over a first side of said substrate;

an aperture formed in said substrate from a second side of said substrate underneath said inductor and extending completely through said substrate from said second side of said substrate to said first side of said substrate;

a dielectric material filling said aperture;

a dielectric material also coating the back side of said substrate; and

an intervening layer between said inductor and said substrate.

7. The circuit of claim 6 wherein said intervening layer is a field oxide region.

8. The circuit of claim 7 wherein said aperture encompasses the entire region beneath said integrated inductor.

9. An integrated circuit comprising:

a semiconductor substrate;

a dielectric layer over said substrate;

an inductor formed over a first side of said substrate over said dielectric layer;

an aperture in said substrate directly underneath said inductor and extending completely through said substrate from said second side of said substrate to said first side of said substrate; and

a dielectric filling said aperture such that the material beneath said inductor is all dielectric material.

10. The circuit of claim 9 wherein said inductor is an integrated inductor.

11. The circuit of claim 10 wherein said dielectric layer includes a field oxide region.

12. The circuit of claim 10 wherein said aperture is formed completely through said substrate to said dielectric layer.

13. The circuit of claim 12 wherein said aperture encompasses the entire region beneath said inductor.