Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics

• US 6,727,588 B1
• Filed: 08/19/1999
• Issued: 04/27/2004
• Est. Priority Date: 08/19/1999
• Status: Expired due to Term
• 

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Abdelgadir, Mahjoub Ali, Yih, Pei H., Merchant, Sailesh Mansinh, Layadi, Nace, Saxena, Vivek
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Owens, Douglas W.
• Application Number:
  US09/377,386
• Time in Patent Office: 1,713 Days
• Field of Search: 257/751, 257/753, 257/758, 257/763
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiO_x, where x is preferably less than 2.

Claims

1. An integrated circuit, comprising:

a substrate having at least one first conductive element disposed thereon;

an impurity containing dielectric layer of fluorosilicate glass disposed over and contacting said substrate and said first conductive element;

an impurity preventing barrier layer disposed over and contacting said impurity containing dielectric layer, wherein said impurity preventing barrier layer includes a silicon rich oxide; and

at least one second conductive element disposed over said impurity preventing barrier layer having at least one surface of said second conductive element contacting said impurity preventing barrier layer.

2. An integrated circuit as recited in claim 1, wherein said impurity containing dielectric layer is a low-k dielectric material.

3. An integrated circuit as recited in claim 1, wherein said impurity preventing barrier layer is disposed in-situ.

4. An integrated circuit as recited in claim 1 wherein said impurity containing dielectric layer contains unbonded or loosely-bonded fluorine radicals and ions.

5. An integrated circuit as recited in claim 1 wherein said at least one conductive element is titanium.

6. An integrated circuit, comprising:

a substrate having at least one first conductive element disposed thereon;

a fluorine doped oxide layer disposed over and contacting said substrate and said first conductive element;

an impurity preventing silicon rich oxide barrier layer disposed over and contacting said fluorine doped oxide layer; and

at least one second conductive element disposed over said impurity preventing silicon rich oxide barrier layer having at least one surface of said second conductive element contacting said impurity preventing silicon rich oxide barrier layer.

7. An integrated circuit as recited in claim 6, wherein said fluorine doped oxide layer is fluorosilicate glass (FSG).

8. An integrated circuit as recited in claim 6, wherein said at least one second conductive element contains metal.

9. An integrated circuit as recited in claim 6, wherein said at least one second conductive element further comprises a stack of at least two layers and a bottom layer of said stack is Ti.

10. An integrated circuit as recited in claim 6, wherein said impurity preventing barrier layer is SiO_x, where x<

2.

11. An integrated circuit as recited in claim 6, wherein said fluorine doped oxide layer is a low-k material.

12. An integrated circuit as recited in claim 6 wherein said fluorine doped oxide layer contains unbonded or loosely-bonded fluorine radicals and ions.

13. An integrated circuit as recited in claim 6 wherein said at least one conductive element is titanium.