Process of testing a semiconductor wafer of IC dies

• US 6,727,722 B2
• Filed: 04/16/2001
• Issued: 04/27/2004
• Est. Priority Date: 10/31/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): KOBERT, RUSSELL MARC
• Application Number:
  US09/835,802
• Publication Number:
  US 20010052787A1
• Time in Patent Office: 1,107 Days
• Field of Search: 324/754, 324/755, 324/765, 324/763, 324/158.1, 439/14, 439/17, 174/260, 174/261, 174/255, 174/267, 361/748, 361/760, 361/767, 361/768, 361/771, 361/777, 361/779
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Integrated circuit die on a wafer are tested individually, without probing any of the die, using circuitry (TC1-8, BC1-8, LR1-8, RR1-8, PA1-PA4) provided on the wafer. The process connects first and second bond pads of a first die to provide a test path through the first die. The process applies a test signal to a second die connected to the second bond pad of the first die. The process passes the test signal from the first bond pad of the first die along the test path through the first die to the second bond pad of the first die and then to the second die.

Claims

1. A process of testing a semiconductor wafer of integrated circuit dies, each of the integrated circuit dies being formed in a rectangular portion of the wafer and the dies being formed in rows and columns with the sides of each die aligned parallel with the sides of adjacent dies, the sides of the dies being separated from one another by scribe lanes between the dies that will be scribed and broken to separate the dies from one another, each die having at least two groups of bond pads with each group of bond pads adjacent opposite sides of the die, each die including functional circuitry for performing normal operating functions, test circuitry for performing testing of the die, and by-pass circuitry for selectively by-passing the functional and test circuitry of the die, the functional circuitry, test circuitry and by-pass circuitry being connected to the groups of bond pads with the by-pass circuitry selectively connecting bond pads on one side of the die with bond pads on the opposite side of the die without activating the functional and testing circuitry, and the wafer including electrical leads formed on the wafer and extending across the scribe lanes to connect a group of bond pads on one side of one die with a group of bond pads on an adjacent side of an adjacent die, the process comprising:

applying a control signal to a first bond pad of a first die;

B. applying test signals to a first group of bond pads of the first die;

C. selectively conducting the test signals received at the first group of bond pads to a second group of bond pads located on an opposite side of the first die to by-pass the functional and test circuitry on the first die; and

D. applying the test to a second die by conveying, on the electrical leads, the test signals at the second group of bond pads on the first die to a first group of bond pads on the second die.

2. The process of claim 1 including selectively applying the test signals to a group of bond pads at an end of each row and column.

3. The process of claim 1 in which the applying test signals includes applying the test signals on a probe test pad formed on the wafer separate from the bond pads of the dies.

4. The process of claim 1 in which each die has at least four groups of bond pads with each group of bond pads adjacent each side of the die, including applying additional test signals to a third group of bond pads on the first die, and selectively conducting the test signals received at the third group of bond pads to a fourth group of bond pads located on an opposite side of the first die to by-pass the functional and test circuitry on the first die.

5. The process of claim 4 including selectively applying the test signals to a group of bond pads at an end of each row and column.

6. The process of claim 4 in which the applying test signals includes applying the test signals on a probe test pad formed on the wafer separate from the bond pads of the dies.

7. A process of testing a semiconductor wafer of integrated circuit dies comprising:

A. applying a control signal to a first bond pad of a first, rectangular die;

B. applying test signals to a first group of bond pads adjacent a side of the first die;

C. selectively conducting, on leads formed on the first die, the test signals received at the first group of bond pads to a second group of bond pads located on an opposite side of the first die to by-pass functional and test circuitry on the first die; and

D. applying the test signals to a second die adjacent the first die by conveying the test signals at the second group of bond pads on the first die to a first group of bond pads on the second die on electrical leads formed on the wafer across scribe lanes between the dies.

8. The process of claim 7 including selectively applying the test signals to a group of bond pads at the end of a row of the dies and to a group of bond pads at the end of a column of the dies.

9. The process of claim 7 in which the applying test signals to the first die includes applying the test signals on a probe test pad formed on the wafer separate from the bond pads of the dies.

10. The process of claim 7 including applying additional test signals to a third group of bond pads on the first die, and selectively conducting the test signals received at the third group of bond pads to a fourth group of bond pads located on an opposite side of the first die to by-pass the functional and test circuitry on the first die.

11. The process of claim 10 including selectively applying the test signals to a group of bond pads at an end of each row and column.

12. The process of claim 10 in which the applying test signals includes applying the test signals on a probe test pad formed on the wafer separate from the bond pads of the dies.