Test system and manufacturing of semiconductor device

• US 6,727,723 B2
• Filed: 05/08/2002
• Issued: 04/27/2004
• Est. Priority Date: 11/19/1999
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Shimizu, Isao, Fukiage, Hiroshi, Sato, Masayuki
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): KERVEROS, JAMES C
• Application Number:
  US10/140,043
• Publication Number:
  US 20020171449A1
• Time in Patent Office: 720 Days
• Field of Search: 324/765, 324/754, 324/755, 324/158.1, 324/758, 324/757, 324/760, 324/761, 324/763
• US Class Current: 324/750.05
• CPC Class Codes: G01R 31/2806 Apparatus therefor, e.g. test stations, drivers, analysers, conveyors G01R31/2805, G01R31/281, G01R31/2818 take precedence
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A test circuit is provided on a probe card or a wafer on which semiconductor chips to be tested are formed. The test circuit and each of the semiconductor chips to be tested are electrically connected to each other to perform testing, whereby the test can be carried out without using a tester. Conducting a test in such a wafer stage within an aging device allows the simplification or omission of a test subsequent to packaging.

Claims

1. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps of:

forming a plurality of semiconductor chips each having a desired function on a semiconductor wafer;

placing a test circuit connected to needles and operated in accordance with a program to test said each semiconductor chip, on a probe substrate having a size corresponding to the semiconductor wafer and having the conductive needles formed thereon in alignment with the placement of electrode pads on the semiconductor chips;

superimposing the probe substrate on the semiconductor wafer in such a manner that the needles are brought into contact with the corresponding electrode pads of the semiconductor chips;

testing said each semiconductor chip by the test circuit; and

selecting a semiconductor chip judged to be non-defective, as a product according to the test.

2. The method according to claim 1, wherein programmable logic ICs capable of configuring arbitrary logic are provided on the probe substrate in association with the respective semiconductor chips on the wafer, and the test circuit is configured within said each programmable logic IC based on the design data for said each semiconductor chip, which is described in hardware description language, and said each semiconductor chip is tested by the test circuit.

3. The method according to claim 2, wherein said test circuit is a test signal generating circuit configured so as to generate a test signal to each semiconductor chip to be tested in accordance with a predetermined algorithm.

4. The method according to claim 3, wherein said test signal generating circuit includes a memory which holds a program therein, a controller which decodes an instruction for the program to thereby generate a control signal, and a signal generator which generates a signal to be outputted.

5. The method according to claim 4, wherein said memory is a rewritable memory.

6. The method according to claim 4, wherein said test signal generating circuit further includes timing generating means which generates a desired a reference clock signal as well as timing control data outputted from memory means for holding the timing control data.

7. The method according to claim 6, wherein said memory means is a rewritable memory.

8. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps of:

forming a test circuit module which is operated in accordance with a program and tests each of a plurality of semiconductor chips, on a semiconductor wafer on which said plurality of semiconductor chips are formed;

supplying a source voltage to at least said test circuit module from the outside to thereby test said each semiconductor chip on the semiconductor wafer by said test circuit module; and

selecting the semiconductor chip judged to be non-defective by said test, as a product.

9. The method according to claim 8, wherein connections between said test circuit module and semiconductor chips to be tested are carried out by probe means which has a size corresponding to the wafer with the semiconductor chips formed thereon and which is provided with conductive needles aligned with the placement of the teat circuit module and electrode pads of the semiconductor chips, and wirings which connect between the predetermined needles.

10. The method according to claim 8, wherein the connections between said test circuit module and the semiconductor chips to be tested are carried Out by wirings farmed in a scribe area of the wafer or a test-dedicated wiring layer.

11. The method according to claim 10, wherein the test wirings for connecting between said test circuit module and the semiconductor chips to be tested are wirings formed within the scribe area of the wafer so as to meander.

12. The method according to claim 8, wherein the test on said each semiconductor chip by said test circuit module is carried out during burn-in or aging processing.

13. The method according to claim 8 further comprising the steps of:

describing the function of said each semiconductor chip to be tested in hardware description language, inputting the hardware description and a test program to a hardware emulator, and simulating the same by the hardware emulator, thereby performing verification thereof;

thereafter converting the hardware description to design data of a logic gate level and generating layout design data of a device level for said each tested semiconductor chip, based on the design data;

extracting a test function, based on the data used in the simulation, describing the test function in hardware description language, converting the description to design data of a logic gate level, and generating layout design data of a device level of said test circuit module, based on the design data;

fabricating a wafer mask by using the layout design data of the device level for said each tested semiconductor chip and the layout design data of the device level for the test circuit module; and

forming said tested semiconductor chip and said test circuit module on one wafer by using the mask.

14. The method according to claim 8, wherein said test circuit module generates test signals supplied to a plurality of the semiconductor chips placed therearound.

15. The method according to claim 8, wherein said test circuit module tests the plurality of semiconductor chips on the semiconductor wafer.