Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array

• US 6,727,726 B1
• Filed: 11/12/2002
• Issued: 04/27/2004
• Est. Priority Date: 11/12/2002
• Status: Expired due to Term

• Current Assignee: Microsemi SoC Corp. (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Plants, William C.
• Primary Examiner(s): LE, DON P
• Application Number:
  US10/293,895
• Time in Patent Office: 532 Days
• Field of Search: 326/37-41, 326/82, 326/83, 326/86
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

The present system comprises a device and a method for increasing the performance and utilization in a field programmable gate array (FPGA). The device of the present system comprises an FPGA having logic clusters, wherein each logic cluster further comprises a buffer. The method of the present system comprises a method of determining which buffers situated in each logic cluster are located in the best position in the post-placement user netlist to decrease the capacitance in the user netlist.

Claims

1. A field programmable gate array having a plurality of logic clusters coupled through a multilevel routing structure having at least a first level and a second level by programmable elements, said logic clusters comprising:

a plurality of logic modules

at least one flip flop;

a receiver configured to transfer signals from said second level to said first level of said multilevel routing structure;

a transmitter configured to transfer signals within said second level of said multilevel routing structure and configured to transfer a signal from said first level to said second level of said multilevel routing structure; and

a load-capacitance-management buffer configured to drive signals within said first level of said multilevel routing structure, wherein said load-capacitance-management buffer is programmably coupled to said first level of said multilevel routing structure via at least one programmable element.

2. The logic cluster of claim 1 wherein said at least one load-capacitance-management buffer module comprises a two-input AND gate.

3. A field programmable gate array comprising:

a plurality of interconnect conductors;

a plurality of programmable elements;

a plurality of input/output modules;

a plurality of logic clusters, said logic clusters comprising a plurality of logic modules, a plurality of receiver modules, a plurality of transmitter modules, a plurality of flip-flops and at least one load-capacitance-management buffer; and

a multi-level routing structure that couples together said logic clusters through plurality of interconnect conductors and said plurality of programmable elements to said plurality of input/output modules.

4. The field programmable gate array of claim 3 wherein the plurality of programmable elements comprise antifuses.

5. The field programmable gate array of claim 3 wherein the buffer module comprises a two-input AND gate.

6. A method of constructing a field programmable gate array having a plurality of logic clusters coupled through a multilevel routing structure having at least a first level and a second level by programmable elements, said logic clusters comprising:

providing a plurality of logic modules

providing at least one flip flop;

providing a receiver configured to transfer signals from said second level to said first level of said multilevel routing structure;

providing a transmitter configured to transfer signals within said second level of said multilevel routing structure and configured to transfer a signal from said first level to said second level of said multilevel routing structure; and

providing a load-capacitance-management buffer configured to drive signals within said first level of said multilevel routing structure, wherein said load-capacitance-management buffer is programmably coupled to said first level of said multilevel routing structure via a programmable element.

7. The logic cluster of claim 6 wherein said at least one load-capacitance-management buffer module comprises a two-input NAND gate.

8. A method of placing buffers into an FPGA circuit comprised of a plurality of logic clusters, each of said logic clusters having buffer modules, comprising:

inputting a function netlist defining a user circuit;

optimizing said user circuit;

placing the function netlist defining the user circuit into said logic clusters;

analyzing said function netlist to determine selection of said buffer modules in said user circuit;

selecting at least one of said buffers for a post-placement function netlist;

including said at least one of said buffers in said post-placement netlist;

defining a routing structure to interconnect said logic clusters to implement said user circuit;

generating a programming data file; and

programming said logic clusters with said programming data file.

9. The method of claim 8 wherein said load-capacitance-management buffer modules further comprise a two-input AND gate.

10. An apparatus for inserting load-capacitance-management buffers into a post-placement user function netlist in an FPGA circuit comprised of a plurality of logic clusters, each of said logic clusters having buffer modules, comprising:

means for inputting a function netlist defining a user circuit;

means for optimizing said user circuit;

means for placing user cells into said FPGA logic clusters;

means for analyzing said function netlist to determines selection of said load-capacitance-management buffer modules;

means for selecting at least one of said load-capacitance-management buffers for a post-placement function netlist;

means for including said at least one of said load-capacitance-management buffers in said post-placement netlist;

means for defining a routing structure to interconnect said logic clusters to implement said user circuit;

means for generating a programming data file; and

means for programming said logic clusters with said programming data file.

11. The apparatus of claim 10 wherein said load-capacitance-management buffer modules further comprise a two-input AND gate.

12. A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for inserting load-capacitance-management buffers into a post-placement user function netlist in an FPGA circuit comprised of a plurality of logic clusters, each of said logic clusters having buffer modules, said method comprising:

inputting a function netlist defining a user circuit;

optimizing said user circuit;

placing the function netlist defining the user circuit into said logic clusters;

analyzing said function netlist to determine selection of said load-capacitance-management buffer modules in said user circuit;

selecting at least one of said load-capacitance-management buffers for a post-placement function netlist;

including said at least one of said load-capacitance-management buffers in said post-placement netlist;

defining a routing structure to interconnect said logic clusters to implement said user circuit;

generating a programming data file; and

programming said logic clusters with said programming data file.