Switched capacitor summing system and method

• US 6,727,749 B1
• Filed: 08/29/2002
• Issued: 04/27/2004
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Quinn, Patrick J.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): COX, CASSANDRA F
• Application Number:
  US10/232,113
• Time in Patent Office: 607 Days
• Field of Search: 330/9, 330/69, 330/147, 327/124, 327/337, 327/361
• US Class Current: 330/9
• CPC Class Codes: G06G 7/14 for addition or subtraction of vector quantities G06G7/22 ; computing the average by addition; differential amplifiers H03F3/45
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06

Abstract

An apparatus and method for adding input voltage signals. First and second input voltage signals are respectively sampled onto first and second capacitors during a first clock phase. In response to a second clock phase, the first sampled input voltage that is held on the first capacitor is coupled to the negative input terminal of an amplifier, and the second sampled voltage held on the second capacitor is coupled to the positive terminal of the amplifier. A feedback voltage is provided from the amplifier output to the negative amplifier input via the first capacitor during the second clock phase. The first and second input voltage signals are added at the amplifier during the second clock phase to output the sum in response to the sampled input voltage signals and the output feedback, whereby the resulting transfer function is independent of capacitor mismatch and non-linearity.

Claims

1. A circuit for adding a plurality of input signals, comprising:

an amplifier having inverting and non-inverting input terminals and an output terminal;

a first sampling circuit coupled between a first input signal and a first reference signal to store a first voltage across a first capacitor in response to a first clock phase;

a second sampling circuit coupled between a second input signal and a second reference signal to store a second voltage across a second capacitor in response to the first clock phase; and

a switching circuit coupled to the amplifier and the first and second sampling circuits, wherein, in response to a second clock phase, the switching circuit switches the first capacitor storing the first voltage between the inverting input terminal and the output terminal of the amplifier, and further switches the second capacitor storing the second voltage between the non-inverting input terminal and a third input signal.

2. The circuit of claim 1, further comprising an N-phase clock signal comprising the first and second clock phases and remaining clock phases of the N-phase clock signal, and wherein the switching circuit switches the first capacitor between the inverting input terminal and the output terminal of the amplifier, and switches the second capacitor between the non-inverting input terminal and a third input signal, in response to selected ones of the second and remaining clock phases of the N-phase clock signal.

3. The circuit of claim 1, wherein the first reference signal comprises a DC reference voltage.

4. The circuit of claim 1, wherein the first reference signal comprises a time-varying signal.

5. The circuit of claim 1, wherein the second reference signal comprises a DC reference voltage.

6. The circuit of claim 1, wherein the second reference signal comprises a time-varying signal.

7. The circuit of claim 1, wherein the first and second reference signals comprises a common DC reference voltage.

8. The circuit of claim 1:

(a) further comprising;

(i) a third sampling circuit coupled between the first input signal and the first reference signal to store a third voltage across a third capacitor in response to the second clock phase;

(ii) a fourth sampling circuit coupled between the second input signal and the second reference signal to store a fourth voltage across a fourth capacitor in response to the second clock phase; and

(b) wherein the switching circuit is further coupled to the third and fourth sampling circuits, wherein, in response to the first clock phase, the switching circuit switches the third capacitor storing the third voltage between the inverting input terminal and the output terminal of the amplifier, and further switches the fourth capacitor storing the fourth voltage between the non-inverting input terminal and the third input signal.

9. The circuit of claim 8, wherein:

the output terminal of the amplifier outputs a first output signal representative of a sum of the first and second voltages offset by the third input signal; and

the output terminal of the amplifier outputs a second output signal representative of a sum of the third and fourth voltages offset by the third input signal, at alternating clock phases from the output of the first output signal.

10. The circuit of claim 1, wherein the output terminal of the amplifier outputs a signal representative of a sum of the first and second voltages, offset by the third input signal.

11. A circuit for adding a plurality of input signals, comprising:

(a) an amplifier having inverting and non-inverting input terminals and an output terminal;

(b) a plurality of sampling circuit pairs, each of the sampling circuit pairs comprising;

(i) a first capacitor coupled between a first input signal and a first reference signal on which to store across a first voltage in response to a first clock phase;

(ii) a second capacitor coupled between a second input signal and a second reference signal on which to store across a second voltage in response to the first clock phase;

(c) a plurality of switching circuits, each coupled to the amplifier and to the first and second sampling circuits of one of the sampling circuit pairs, wherein, in response to a second clock phase, each switching circuit switches the first capacitor storing the first voltage between the inverting input terminal and the output terminal of the amplifier, and further switches the second capacitor storing the second voltage between the non-inverting input terminal and a third input signal;

(d) wherein the first and second clock phases for each sampling circuit pair and corresponding switching circuit are offset relative to other sampling circuit pairs and corresponding switching circuits, and wherein the amplifier adds the first and second voltages, offset by the third input signal, for each sampling circuit pair and corresponding switching circuit.

12. A circuit for adding a plurality of input signals, comprising:

an amplifier having first and second input terminals and an output terminal;

a first capacitance coupled to receive a first input signal and to store a corresponding first voltage across the first capacitance in response to a first clock phase;

a second capacitance coupled to receive a second input signal and to store a corresponding second voltage across the second capacitance in response to the first clock phase;

a first switch circuit coupled to the first capacitance to provide the first voltage to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop, in response to a second clock phase; and

a second switch circuit coupled to the second capacitance to provide the second voltage to the second input terminal of the amplifier in response to the second clock phase.

13. The circuit of claim 12, wherein the second switch circuit is further coupled to receive a shift signal during the second clock phase, wherein the shift signal is subtracted from the sum of the first and second input signals at the output of the amplifier.

14. The circuit of claim 13, wherein:

the first capacitance comprises at least one capacitor component having a top plate and a bottom plate;

the top plate of the capacitor component is coupled to a third input signal via the first switch circuit during the first clock phase and to the first input terminal of the amplifier via the first switch circuit during the second clock phase; and

the bottom plate of the capacitor component is coupled to the first input signal through the first switch circuit during the first clock phase and to the output terminal of the amplifier via the first switch circuit during the second clock phase.

15. The circuit of claim 13, wherein:

the second capacitance comprises at least one capacitor component having a top plate and a bottom plate;

the top plate of the capacitor component is coupled to a fourth input signal via the second switch circuit during the first clock phase and to the second input terminal of the amplifier via the second switch circuit during the second clock phase; and

the bottom plate of the capacitor component is coupled to the second input signal through the second switch circuit during the first clock phase and to a level shifting voltage via the second switch circuit during the second clock phase.

16. The circuit of claim 12, wherein the first input terminal of the amplifier is a negative input terminal, and the second input terminal of the amplifier is a positive input terminal.

17. The circuit of claim 12, wherein the first and second capacitance are substantially electrically isolated from each other via an impedance between the first and second input terminals of the amplifier.

18. The circuit of claim 12, wherein the first and second capacitances comprise components that exhibit capacitance capable of respectively storing the first and second voltages thereon.

19. The circuit of claim 12, wherein one or more of the first and second input signals are substantially direct current (DC) voltage signals.

20. The circuit of claim 12, wherein one or more of the first and second input signals are time varying voltage signals.

21. The circuit of claim 12, wherein the output terminal of the amplifier outputs an output voltage corresponding to a sum of the first and second input signals independent of a ratio of the first and second capacitances.

22. A circuit for adding a plurality of input signals, comprising:

an amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal;

means for sampling a first input signal onto a plurality of first capacitors at different phases of a multi-phase clock;

means for sampling a second input signal onto a plurality of second capacitors at different phases of a multi-phase clock; and

means for alternately providing each pair of the first and second sampled input signals to the inverting and non-inverting input terminals of the amplifier on a common phase of the multi-phase clock, wherein each of the pairs of the first and second sampled input signals are provided to the amplifier on a different phase of the multi-phase clock relative to the other pairs of the first and second sampled input signals.

23. The circuit of claim 22, further comprising means for level shifting the added first and second sampled input signals at the output of the amplifier.

24. A method for adding at least two input voltage signals, comprising:

sampling first and second input voltage signals onto first and second capacitor circuits respectively during a first clock phase;

coupling the first sampled input voltage held on the first capacitor circuit to a negative input terminal of an amplifier, and coupling the second sampled input voltage held on the second capacitor circuit to a positive input terminal of the amplifier, during a second clock phase;

providing a feedback voltage from an output of the amplifier to the negative input of the amplifier via the first capacitor circuit during the second clock phase; and

outputting a sum of the first and second input voltage signals in response to the feedback voltage and the first and second sampled input voltages during the second clock phase.

25. The method of claim 24, further comprising shifting the voltage level at the output during the second clock phase by applying a shift level voltage to the second capacitor circuit to algebraically modify the second sampled input voltage present at the positive input terminal of the amplifier.

26. The method of claim 24, further comprising activating at least one switch to create an electrical connection between the second capacitor circuit and the shift level voltage in response to the second clock phase.

27. The method of claim 24, further comprising:

sampling the first and second input voltage signals onto third and fourth capacitor circuits respectively during the second clock phase;

coupling the first sampled input voltage held on the third capacitor circuit to the negative input terminal of the amplifier, and coupling the second sampled input voltage held on the fourth capacitor circuit to the positive input terminal of the amplifier, during the first clock phase;

providing a second feedback voltage from the output of the amplifier to the negative input of the amplifier via the third capacitor circuit during the first clock phase; and

outputting a sum of the first and second input voltage signals in response to the second feedback voltage and the first and second sampled input voltages during the first clock phase.

28. The method of claim 27, further comprising shifting the voltage level at the output during the second clock phase by applying a shift level voltage to the second capacitor circuit to algebraically modify the second sampled input voltage present at the positive input terminal of the amplifier.

29. The method of claim 27, further comprising shifting the voltage level at the output during the first clock phase by applying a shift level voltage to the fourth capacitor circuit to algebraically modify the second sampled input voltage present at the positive input terminal of the amplifier.

30. The method of claim 24, wherein the first and second clock phases comprise non-overlapping complementary clock phases.

31. The method of claim 24, wherein the first and second capacitor circuits are substantially electrically isolated from one another via input impedances at the negative and positive input terminals of the amplifier.

32. The method of claim 24, wherein coupling the first sampled input voltage held on the first capacitor circuit to the negative input terminal of the amplifier comprises activating at least one switch in response to the second clock phase to create an electrical connection between the first capacitor circuit and the negative input terminal of the amplifier.

33. The method of claim 24, wherein coupling the second sampled input voltage held on the second capacitor circuit to the positive input terminal of the amplifier comprises activating at least one switch in response to the second clock phase to create an electrical connection between the second capacitor circuit and the positive input terminal of the amplifier.

34. The method of claim 24, wherein sampling first and second input voltage signals onto first and second capacitor circuits respectively comprises sampling the first and second input voltage signals onto bottom plates of first and second capacitors respectively.

35. The method of claim 34, further comprising coupling a top plate of the first and second capacitors to respective first and second reference voltages during the first clock phase.

36. The method of claim 34, further comprising coupling a top plate of the first and second capacitors to a common reference voltage during the first clock phase.