High-definition liquid crystal display including sub scan circuit which separately controls plural pixels connected to the same main scan wiring line and the same sub scan wiring line

• US 6,727,875 B1
• Filed: 10/12/2000
• Issued: 04/27/2004
• Est. Priority Date: 10/13/1999
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Aono, Yoshinori, Mikami, Yoshiro, Kageyama, Hiroshi, Satou, Hideo
• Primary Examiner(s): NGUYEN, CHANH DUY
• Application Number:
  US09/686,947
• Time in Patent Office: 1,293 Days
• Field of Search: 345/87, 345/92, 345/90, 345/91, 345/93, 345/98, 345/100, 345/103, 349/48, 349/41, 349/42, 349/46, 349/33
• US Class Current: 345/92
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2320/02 Improving the quality of display appearance
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

In a display matrix in which individual pixels in which a sub scan wiring and a display electrode, a main circuit of TFT controlled by an applied voltage of the main scan wiring and the sub scan wiring, and signal wiring and a display electrode are connected in series are arranged, and the sub scan wiring is arranged in the vertical direction, a line is selected and driven with the main scan pulse shifted sequentially in the individual frame time supplied on the main scan wiring, and with the sub scan pulse varying its state in a time of the main scan pulse.

Claims

1. A liquid crystal display apparatus, comprising:

plural main scan wiring lines;

signal wiring lines arranged so as to intersect with the plural main scan wiring lines;

a display matrix having one or more sub scan wiring lines arranged along the plural signal wiring lines;

plural pixels arranged in a column direction in an area partitioned by the main scan wiring lines and the signal wiring lines, the plural pixels being formed with plural pixel TFT devices; and

a display electrode;

wherein one end of a main circuit of the plural pixel TFT devices is connected to a display electrode in a corresponding pixel, and its other end is connected to a signal wiring line;

wherein at least one of the gate electrodes of the plural pixel TFT devices is connected to a main scan wiring line, and the remaining gate electrodes are connected to an identical sub scan wiring line in a row direction; and

wherein the liquid crystal apparatus further comprises;

a main scan circuit for selecting and driving sequentially the main scan wiring lines, and a sub scan circuit for driving the sub scan wiring line;

a signal circuit for supplying an image signal to the signal wiring lines in synchronization with a main scan signal and a sub scan signal; and

an opposed substrate power circuit for applying a voltage to an opposed electrode facing plural display electrodes and supporting a liquid crystal;

wherein a pair of TFT devices are connected to a signal wiring line and a display electrode by a series connection, and one of the gate electrodes of the pair of TFT devices is connected to a main scan wiring line assigned to every two pixels in a row direction, and the other gate electrode thereof is connected to the sub scan wiring line assigned to a single signal wiring line; and

wherein a row of pixels are selected and driven in response to a main scan signal and a sub scan signal.

2. A liquid crystal display apparatus according to claim 1,

wherein three TFT devices are connected in each pixel to the signal wiring lines and the display electrode by a series connection; and

wherein a main scan wiring line is provided for four rows of pixels, and the polarity of the three TFT devices is defined by repetitive and cyclic use of patterns, Nch-Nch-Nch, Nch-Nch-Pch, Nch-Pch-Nch and Nch-Pch-Pch, wherein each Nch device at the first one of the gate electrodes of the three TFT devices is connected in common to the main scan wiring line, while, for the other two TFTs, the second ones have their gates connected to each other and the third ones have their gates connected to each other, and then each is connected individually to respective ones of two sub scan wiring lines.