DMA channel for high-speed asynchronous data transfer
First Claim
1. An apparatus for communicating high speed asynchronous data, comprising:
- a DMA controller;
a DMA FIFO memory coupled to the DMA controller;
a transmitter/receiver for transmitting and receiving data, the transmitter/receiver is coupled to the DMA controller via the DMA FIFO memory; and
a timer configured to time an expiration time, the timer configured to receive a reset signal from the transmitter/receiver to start timing of the expiration time, and the timer configured to communicate a signal to the DMA controller at the end of the expiration time, such that at least one byte of information is communicated out of the DMA FIFO memory.
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Abstract
An apparatus and method for transferring high speed asynchronous data using a DMA controller. By using a conventional Universal Serial Asynchronous Receiver Transmitter (USART) with a small buffer, high speed asynchronous data can be manipulated by the DMA controller by use by other applications, such as wireless communication applications. The wireless communication applications includes Global System for Mobile communications (GSM), Code Division Multiple Access (CDMA), or Personal Digital Cellular (PDC). These wireless communication applications utilize high asynchronous data rates that would require more expensive USART with additional buffer capacity. In the receive mode, the high speed asynchronous data shifted into a DMA FIFO buffer from the USART. The data is then flushed into a host memory, such as a protocol stack by the DMA controller once the FIFO is full or if a timer expires. The data in the protocol stack is then manipulated by the wireless communication application. In the transmit mode, the high speed asynchronous data is similarly manipulated to provide data from the protocol stack to the USART.
The present invention utilizes conventional hardware thus reducing cost and use of chip real estate.
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Citations
47 Claims
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1. An apparatus for communicating high speed asynchronous data, comprising:
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a DMA controller;
a DMA FIFO memory coupled to the DMA controller;
a transmitter/receiver for transmitting and receiving data, the transmitter/receiver is coupled to the DMA controller via the DMA FIFO memory; and
a timer configured to time an expiration time, the timer configured to receive a reset signal from the transmitter/receiver to start timing of the expiration time, and the timer configured to communicate a signal to the DMA controller at the end of the expiration time, such that at least one byte of information is communicated out of the DMA FIFO memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A method for receiving high speed asynchronous data, comprising the steps of:
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(1) receiving the high speed asynchronous data into a receiver;
(2) shifting the high speed asynchronous data into a DMA FIFO memory;
(3) resetting a timer to start timing of an expiration time; and
(4) transferring the high speed asynchronous data from the DMA FIFO memory to a host memory via a DMA controller at least by the end of the expiration time. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35)
receiving a GSM control frame into a receiver;
shifting at least one byte of control data corresponding to the GSM control frame into the DMA FIFO memory;
resetting a second timer to start timing of a second expiration time; and
transferring the at least one byte of control data from the DMA FIFO memory to a host memory via a DMA controller at least by the end of the second expiration time.
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34. The method of claim 30, wherein the high speed asynchronous data is GSM data.
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35. The method of claim 33, wherein the second time period is less than 20 ms.
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36. A method for transmitting high speed asynchronous data, comprising the steps of:
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(1) transferring the high speed asynchronous data from a host memory to a DMA FIFO memory via a DMA controller at a time certain;
(2) resetting a timer to start timing of an expiration time;
(3) shifting the high speed asynchronous data from the DMA FIFO memory to a transmitter at least by the end of the expiration time; and
(4) transmitting the high speed asynchronous data. - View Dependent Claims (37, 38, 39, 40, 41)
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42. A wireless telephone, comprising:
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a DMA controller;
a DMA FIFO memory coupled to the DMA controller;
a host memory coupled to the DMA controller; and
a transmitter/receiver for transmitting and receiving data, the transmitter/receiver coupled to the DMA controller via the DMA FIFO memory; and
a timer configured to time an expiration time, configured to receive a reset signal from the transmitter/receiver to start timing of the expiration time, and configured to communicate a signal to the DMA controller at the end of the expiration time such that at least one byte of information is communicated out of the DMA FIFO memory to the host memory. - View Dependent Claims (43, 44, 45, 46, 47)
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Specification