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DMA channel for high-speed asynchronous data transfer

  • US 6,728,795 B1
  • Filed: 04/17/2000
  • Issued: 04/27/2004
  • Est. Priority Date: 04/17/2000
  • Status: Expired due to Term
First Claim
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1. An apparatus for communicating high speed asynchronous data, comprising:

  • a DMA controller;

    a DMA FIFO memory coupled to the DMA controller;

    a transmitter/receiver for transmitting and receiving data, the transmitter/receiver is coupled to the DMA controller via the DMA FIFO memory; and

    a timer configured to time an expiration time, the timer configured to receive a reset signal from the transmitter/receiver to start timing of the expiration time, and the timer configured to communicate a signal to the DMA controller at the end of the expiration time, such that at least one byte of information is communicated out of the DMA FIFO memory.

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