Hybrid data I/O for memory applications

• US 6,728,799 B1
• Filed: 01/13/2000
• Issued: 04/27/2004
• Est. Priority Date: 01/13/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Eldredge, Kenneth J., Perner, Frederick A.
• Primary Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US09/483,383
• Time in Patent Office: 1,566 Days
• Field of Search: 710/52, 710/36, 371/22.31
• US Class Current: 710/52
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1036 using data shift registers

Abstract

Some forms of memory data I/O requires a parallel interface with the memory array and a serial interface with external data ports to the memory. A hybrid decoder/scan register data I/O scheme is described that offers a high speed data access to selected points along a set of scan registers that connect to the columns (bit lines) of a memory array. The interface to the memory array is a long register which comprises a chain of scan register blocks. Data to and from the memory array is transferred in a parallel manner. Data I/O to a specific memory address or memory data block is routed from a serial data I/O line, through a set of switches controlled by a decoder circuit to the input (or output) port of one of the scan register blocks. This hybrid data I/O circuit offers a high speed access to selected points within the column circuits of a memory array while maintaining an efficient and high speed serial output offered by a scan chain data register.

Claims

1. A data input/output circuit, comprising:

register circuit comprising a plurality of data registers that form shift register blocks, wherein each data register comprises a plurality of scan cells comprising a data shift input, a data shift output and a shift clock input, and wherein the data shift inputs and outputs of the scan cells are coupled to pass data through the register circuit in sequence according to signals at the shift clock input, the couplings between data registers forming data access nodes; and

an I/O control circuit having an address bus input, the I/O control circuit including a plurality of transmission gate circuits coupling the respective data access nodes to a data input/output port, the I/O control circuit also including selection circuitry coupled to the transmission gate circuits for selecting one of the transmission gate circuits on the basis of input on the address bus, so as to enable data to pass between the data register circuit and the input/output port through the selected transmission gate and for shifting data through the scan cells until required data appears at the input/output port.

2. A data input/output circuit as claimed in claim 1, wherein the data register circuit includes a parallel data input/output path, for reading data from and/or writing data to the scan cells of the data register circuit.

3. A data input/output circuit as claimed in claim 2, wherein the parallel data input/output path is coupled to a memory array, such that respective bitlines of the memory array are coupled to respective scan cells of the data register circuit.

4. A data input/output circuit as claimed in claim 1, wherein each of the shift register blocks has an equal number of scan cells.

5. A method for data transfer, comprising:

providing a register circuit having a chain of data registers, wherein each data register has a plurality of scan cells, a data shift input, a data shift output and a shift clock input, and wherein the data shift inputs and outputs of the scan cells are coupled to pass data through the data register according to signals at the shift clock input, the couplings between data shift inputs and outputs forming data access nodes;

selecting one of the data access nodes on the basis of input on the address bus, so as to enable data to pass between the data register circuit and the input/output port; and

transferring data into or out of the data register through the selected data access node by shifting data in the data register using said shift clock input.

6. A method as claimed in claim 5, including a step of parallel input or output of data to or from the scan cells of the data register.

7. A method as claimed in claim 6, wherein selected data is provided by parallel input to the data register from an external data source, and at least a portion of the selected data is serially output through the selected data access node by shifting data in the data register using said shift clock input.

8. A method as claimed in claim 6, wherein selected data is serially input to the data register through the selected data access node by shifting data in the data register using said shift clock input, and the selected data is provided by parallel output from the data register.

9. A method as claimed in claim 8, wherein data is transferred in parallel fashion between the data register and a memory array, respective scan cells being arranged to transfer data by respective bitlines of the memory array.

10. A data input/output circuit for a memory array, comprising:

a data register circuit comprising a sequence of data register blocks, wherein each data register block has a plurality of scan cells, a data shift input, a data shift output and a shift clock input, and wherein the data shift inputs and outputs of the data register blocks are coupled to pass data through the register circuit in sequence according to signals at the shift clock input, the couplings between data shift inputs and outputs forming data access nodes, the data register circuit further including parallel data transfer connections for coupling the register cells to respective bitlines of the memory array; and

an I/O control circuit having an address bus input, the I/O control circuit including a plurality of transmission gate circuits coupling the respective data access nodes to a data input/output port, the I/O control circuit also including selection circuitry coupled to the transmission gate circuits for selecting one of the transmission gate circuits on the basis of input on the address bus, so as to enable data to pass between the data register circuit and the input/output port through the selected transmission gate and for shifting data through the scan cells until required data appears at the input/output port.