Interconnection architecture for managing multiple low bandwidth connections over a high bandwidth link

• US 6,728,803 B1
• Filed: 02/11/2000
• Issued: 04/27/2004
• Est. Priority Date: 03/30/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.), International Business Machines Corporation
• Original Assignee: Mcdata Corporation (Broadcom, Inc.)
• Inventors: Huang, Catherine C., Flanagan, John R., Ricci, Louis W., Casper, Daniel F., Nelson, Jeffrey J., Flauaus, Gary R., Elliott, Joseph C.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): DU, THUAN N
• Application Number:
  US09/502,947
• Time in Patent Office: 1,537 Days
• Field of Search: 710/36, 710/38, 710/58, 710/60, 370/398, 370/465, 370/466, 370/441, 370/442
• US Class Current: 710/60
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A data communication architecture including a plurality of devices having input/output (I/O) ports supporting communication at a first rate and a data processor having a number of I/O ports where each I/O port supports data communication at a second data rate. The second data rate is at least double the first data rate. A communication link coupled to one of the data processor I/O ports supports the second data rate. A bridge device is coupled to the communication link and to the I/O ports of the plurality of devices. The bridge device translates the communication link at the second data rate to a plurality of communication links at the first data rate, where the plurality of communication links at the first data rate are substantially independent of each other.

Claims

1. A data communication architecture comprising:

a plurality of devices having input/output (I/O) ports supporting communication at a first rate wherein the I/O ports of the plurality of devices support circuit switched communication;

a data processor having a number of I/O ports where each I/O port supports communication at a second data rate, wherein the second data rate is at least double the first data rate and wherein the I/O ports of the data processor support packet switched communication;

a communication link coupled to one of the data processor I/O ports and supporting the second data rate;

a bridge device coupled to the communication link and to the I/O ports of the plurality of devices, the bridge device translating the communication link at the second data rate to a plurality of communication links at the first data rate.

2. The data communication architecture of claim 1 wherein the plurality of communication links at the first data rate are substantially independent from each other.

3. The data communication architecture of claim 1 wherein the I/O ports of the plurality of devices support SBCON.

4. The data communication architecture of claim 1 the I/O ports of the data processor support fibre channel.

5. The data communication architecture of claim 1 wherein the data processor generates a plurality of messages where each message is corresponds to a virtual channel with a specific one of the plurality of devices.

6. The data communication architecture of claim 5 further comprising a multiplexer in the data processor coupled to multiplex the plurality virtual channels into a single communication link.

7. The data communication architecture of claim 1 wherein the bridge further comprises:

a front end unit operative as a frame processor;

a local data processor operative to initialize communication link;

a link controller unit comprising a link controller for each of the plurality of devices, each link controller supporting a communication channel with a corresponding one of the plurality of devices.

8. The data communications architecture of claim 7 further comprising:

a first exchange credit mechanism within the local processor operative to generate an exchange credit message to the data processor; and

a second exchange credit mechanism within the data processor operative to receive the exchange credit message.

9. The data communications architecture of claim 7 wherein the first exchange credit mechanism is responsive to the number of operational link controllers in the link controller unit.

10. The data communications architecture of claim 7 wherein the first exchange credit mechanism is responsive to the combined data rate of the plurality of devices that are associated with an operational link controller.

11. The data communications architecture of claim 1, wherein said bridge device comprises:

a packet switched side supporting a full duplex packet switched link;

a circuit switched side supporting a number of full duplex circuit switched links; and

a binding mechanism within the bridge circuit having a storage space for storing a logical binding description binding packet switched frames to a particular one of the circuit switched links.

12. The bridge device of claim 11, wherein the bridge device identifies a logical exchange indicated in packet-switched frames received on the packet switched link and maintains the logical binding throughout the duration of the logical exchange.

13. The bridge device of claim 11, wherein the binding mechanism comprises:

a storage structure holding selected header information from received packet switched frames; and

a frame generator for reformatting received circuit switched frames into packet switched frames using the stored header information.

14. A data communication architecture comprising:

a plurality of devices having input/output (I/O) ports supporting communication at a first rate, wherein the I/O ports of the plurality of devices support circuit switched communication;

a data processor having a number of I/O ports where each I/O port supports communication at a second data rate, wherein the second data rate is at least double the first data rate, wherein the I/O ports of the data processor support packet switched communication, and wherein the data processor generates a plurality of messages where each message corresponds to a virtual channel with a specific one of the plurality of devices;

a communication link coupled to one of the data processor I/O ports and supporting the second data rate; and

a bridge device coupled to the communication link and to the I/O ports of the plurality of devices, the bridge device translating the communication link at the second data rate to a plurality of communication links at the first data rate, wherein the plurality of communication links at the first data rate are substantially independent of each other.

15. A data communication architecture comprising:

a plurality of devices having input/output (I/O) ports supporting communication at a first rate, wherein the I/O ports of the plurality of devices support circuit switched communication;

a data processor having a number of I/O ports where each I/O port supports communication at a second data rate, wherein the second data rate is at least double the first data rate and wherein the I/O ports of the data processor support packet switched communication;

a communication link coupled to one of the data processor I/O ports and supporting the second data rate;

a bridge device coupled to the communication link and to the I/O ports of the plurality of devices, the bridge device translating the communication link at the second data rate to a plurality of communication links at the first data rate;

wherein the bridge device further comprises;

a front end unit operative as a frame processor;

a local data processor operative to initialize communication links; and

a link controller unit comprising a link controller for each of the plurality of devices, each link controller supporting a communication channel with a corresponding one of the plurality of devices.

16. The data communication architecture of claim 15, wherein the data processor generates a plurality of messages where each message corresponds to a virtual channel with a specific one of the plurality of devices and further comprising a multiplexer in the data processor coupled to multiplex the plurality virtual channels into a single communication link.

17. The data communications architecture of claim 15, further comprising:

a first exchange credit mechanism within the local processor operative to generate an exchange credit message to the data processor; and

a second exchange credit mechanism within the data processor operative to receive the exchange credit message.