Interconnection architecture for managing multiple low bandwidth connections over a high bandwidth link
First Claim
1. A data communication architecture comprising:
- a plurality of devices having input/output (I/O) ports supporting communication at a first rate wherein the I/O ports of the plurality of devices support circuit switched communication;
a data processor having a number of I/O ports where each I/O port supports communication at a second data rate, wherein the second data rate is at least double the first data rate and wherein the I/O ports of the data processor support packet switched communication;
a communication link coupled to one of the data processor I/O ports and supporting the second data rate;
a bridge device coupled to the communication link and to the I/O ports of the plurality of devices, the bridge device translating the communication link at the second data rate to a plurality of communication links at the first data rate.
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Abstract
A data communication architecture including a plurality of devices having input/output (I/O) ports supporting communication at a first rate and a data processor having a number of I/O ports where each I/O port supports data communication at a second data rate. The second data rate is at least double the first data rate. A communication link coupled to one of the data processor I/O ports supports the second data rate. A bridge device is coupled to the communication link and to the I/O ports of the plurality of devices. The bridge device translates the communication link at the second data rate to a plurality of communication links at the first data rate, where the plurality of communication links at the first data rate are substantially independent of each other.
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Citations
17 Claims
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1. A data communication architecture comprising:
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a plurality of devices having input/output (I/O) ports supporting communication at a first rate wherein the I/O ports of the plurality of devices support circuit switched communication;
a data processor having a number of I/O ports where each I/O port supports communication at a second data rate, wherein the second data rate is at least double the first data rate and wherein the I/O ports of the data processor support packet switched communication;
a communication link coupled to one of the data processor I/O ports and supporting the second data rate;
a bridge device coupled to the communication link and to the I/O ports of the plurality of devices, the bridge device translating the communication link at the second data rate to a plurality of communication links at the first data rate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
a front end unit operative as a frame processor;
a local data processor operative to initialize communication link;
a link controller unit comprising a link controller for each of the plurality of devices, each link controller supporting a communication channel with a corresponding one of the plurality of devices.
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8. The data communications architecture of claim 7 further comprising:
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a first exchange credit mechanism within the local processor operative to generate an exchange credit message to the data processor; and
a second exchange credit mechanism within the data processor operative to receive the exchange credit message.
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9. The data communications architecture of claim 7 wherein the first exchange credit mechanism is responsive to the number of operational link controllers in the link controller unit.
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10. The data communications architecture of claim 7 wherein the first exchange credit mechanism is responsive to the combined data rate of the plurality of devices that are associated with an operational link controller.
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11. The data communications architecture of claim 1, wherein said bridge device comprises:
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a packet switched side supporting a full duplex packet switched link;
a circuit switched side supporting a number of full duplex circuit switched links; and
a binding mechanism within the bridge circuit having a storage space for storing a logical binding description binding packet switched frames to a particular one of the circuit switched links.
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12. The bridge device of claim 11, wherein the bridge device identifies a logical exchange indicated in packet-switched frames received on the packet switched link and maintains the logical binding throughout the duration of the logical exchange.
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13. The bridge device of claim 11, wherein the binding mechanism comprises:
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a storage structure holding selected header information from received packet switched frames; and
a frame generator for reformatting received circuit switched frames into packet switched frames using the stored header information.
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14. A data communication architecture comprising:
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a plurality of devices having input/output (I/O) ports supporting communication at a first rate, wherein the I/O ports of the plurality of devices support circuit switched communication;
a data processor having a number of I/O ports where each I/O port supports communication at a second data rate, wherein the second data rate is at least double the first data rate, wherein the I/O ports of the data processor support packet switched communication, and wherein the data processor generates a plurality of messages where each message corresponds to a virtual channel with a specific one of the plurality of devices;
a communication link coupled to one of the data processor I/O ports and supporting the second data rate; and
a bridge device coupled to the communication link and to the I/O ports of the plurality of devices, the bridge device translating the communication link at the second data rate to a plurality of communication links at the first data rate, wherein the plurality of communication links at the first data rate are substantially independent of each other.
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15. A data communication architecture comprising:
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a plurality of devices having input/output (I/O) ports supporting communication at a first rate, wherein the I/O ports of the plurality of devices support circuit switched communication;
a data processor having a number of I/O ports where each I/O port supports communication at a second data rate, wherein the second data rate is at least double the first data rate and wherein the I/O ports of the data processor support packet switched communication;
a communication link coupled to one of the data processor I/O ports and supporting the second data rate;
a bridge device coupled to the communication link and to the I/O ports of the plurality of devices, the bridge device translating the communication link at the second data rate to a plurality of communication links at the first data rate;
wherein the bridge device further comprises;
a front end unit operative as a frame processor;
a local data processor operative to initialize communication links; and
a link controller unit comprising a link controller for each of the plurality of devices, each link controller supporting a communication channel with a corresponding one of the plurality of devices. - View Dependent Claims (16, 17)
a first exchange credit mechanism within the local processor operative to generate an exchange credit message to the data processor; and
a second exchange credit mechanism within the data processor operative to receive the exchange credit message.
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Specification