Synchronous memory device

• US 6,728,819 B2
• Filed: 03/14/2002
• Issued: 04/27/2004
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US10/097,336
• Publication Number:
  US 20020147877A1
• Time in Patent Office: 775 Days
• Field of Search: 710/100, 710/305, 711/100, 711/105, 711/111, 365/189.01, 365/189.02, 365/230.01, 365/230.02, 365/230.03, 365/230.06, 365/233
• US Class Current: 710/305
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 : Control signal input circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A synchronous semiconductor memory device including a memory cell array and a plurality of input receivers to sample address information synchronously with respect to a clock signal. The address information includes a row address and a column address. The memory device further includes a plurality of sense amplifiers to sense data from a row of the memory cell array, the row of the memory cell array being identified by the row address. Furthermore, the memory device includes a plurality of column decoders coupled to the plurality of sense amplifiers to access, based on the column address, a plurality of data bits of the data sensed by the plurality of sense amplifiers. In addition, the memory device includes a plurality of output drivers to output the plurality of data bits, the plurality of output drivers outputs a first portion of the plurality of data bits synchronously with respect to a rising edge transition of the first clock signal, and the plurality of output drivers outputs a second portion of the plurality of data bits synchronously with respect to a falling edge transition of the first clock signal.

Claims

1. A synchronous semiconductor memory device including a memory cell array, wherein the memory device comprises:

a plurality of input receivers to sample address information synchronously with respect to a first clock signal, wherein the address information includes a row address and a column address;

a plurality of sense amplifiers to sense data from a row of the memory cell array, wherein the row of the memory cell array is identified by the row address;

a plurality of column decoders, coupled to the plurality of sense amplifiers, to access, based on the column address, a plurality of data bits of the data sensed by the plurality of sense amplifiers; and

a plurality of output drivers to output the plurality of data bits, wherein;

the plurality of output drivers outputs first and second portions of the plurality of data bits, in succession, during a clock cycle of the first clock signal.

2. The memory device of claim 1 wherein the memory cell array includes a plurality of subarrays, and wherein each subarray of the plurality of subarrays includes an array of sense amplifiers.

3. The memory device of claim 2 wherein the plurality of column decoders includes a subset of column decoders in each subarray of the plurality of subarrays.

4. The memory device of claim 2 wherein the plurality of data bits is accessed from a first and a second subarray of the plurality of subarrays.

5. The memory device of claim 2 wherein the plurality of subarrays includes first and second subarrays, wherein the row address identifies a first row in the first subarray and a first row in the second subarray, wherein the row of the memory cell array includes the first rows in each of the first and second subarrays.

6. The memory device of claim 5 wherein the row address further identifies a second row in the first subarray and a second row in the second subarray, wherein the row of the memory cell array further includes the second rows in each of the first and second subarrays.

7. The memory device of claim 5 wherein:

the first subarray includes a decoder to select, based on the row address, the first row in the first subarray; and

the second subarray includes a decoder to select, based on the row address, the first row in the second subarray.

8. The memory device of claim 1 further including a plurality of pins to connect the memory device to an external bus having a plurality of signal lines, wherein a first subset of the plurality of pins connects to the plurality of output drivers, and wherein the plurality of output drivers outputs the plurality of data bits onto a first subset of the plurality of signal lines via the first subset of the plurality of pins.

9. The memory device of claim 8 wherein the address information is sampled from the external bus during a plurality of clock cycles of the first clock signal.

10. The memory device of claim 9 wherein the plurality of input receivers are coupled to a second subset of the plurality of pins to sample the address information from a second subset of the plurality of external signal lines via the second subset of the plurality of pins.

11. The memory device of claim 10 wherein the first subset of the plurality of pins are included in the second subset of the plurality of pins.

12. The memory device of claim 1 wherein the plurality of data bits is output in response to an operation code that specifies a read operation.

13. The memory device of claim 12 wherein the operation code includes precharge information, wherein the precharge information indicates that the plurality of sense amplifiers is precharged, after the plurality of data bits is accessed, without further instruction.

14. The memory device of claim 12 wherein the operation code includes precharge information, wherein the precharge information indicates that the plurality of sense amplifiers retain the data, after the plurality of data bits is accessed, without further instruction.

15. The memory device of claim 12 wherein the operation code is sampled synchronously with respect to the first clock signal.

16. The memory device of claim 15 wherein the operation code is sampled by a subset of the plurality of input receivers.

17. The memory device of claim 1 further including:

a plurality of multiplexers coupled to the plurality of output drivers, wherein the first and second portions of the plurality of data bits are provided to the plurality of output drivers by the plurality of multiplexers; and

a plurality of internal data lines, coupled to the plurality of sense amplifiers and the plurality of multiplexers, to provide the plurality of data bits to the plurality of multiplexers.

18. The memory device of claim 17 wherein the plurality of internal data lines includes an internal data line corresponding to each data bit of the plurality of data bits.

19. The memory device of claim 1 further including a clock receiver to receive the first clock signal, wherein the first clock signal is an externally provided periodic signal.

20. The memory device of claim 19 further including a delay locked loop, coupled to the plurality of output drivers and the clock receiver, to synchronize output of the first and second portions of the plurality of data bits with the first clock signal.

21. The memory device of claim 20 wherein the delay locked loop includes:

a delay line to generate an internal clock signal, wherein the internal clock signal has a delay with respect to the first clock signal; and

a comparator to compare the internal clock signal with the first clock signal, wherein the delay of the internal clock signal is controlled based on the comparison between the internal clock signal and the first clock signal.

22. The memory device of claim 21 further including a plurality of multiplexers coupled to the plurality of output drivers and the delay locked loop, wherein:

the plurality of multiplexers provides the first portion of the plurality of data bits to the plurality of output drivers in response to a rising edge transition of the first clock signal; and

the plurality of multiplexers provides the second portion of the plurality of data bits to the plurality of output drivers in response to a falling edge transition of the first clock signal.

23. The memory device of claim 20 wherein the delay locked loop generates a first internal clock signal and a second internal clock signal, wherein the first and second internal clock signals are complementary, and wherein the memory device further includes a plurality of multiplexers coupled to the plurality of output drivers and the delay locked loop, wherein:

the plurality of multiplexers provides the first portion of the plurality of data bits to the plurality of output drivers in response to a transition of the first internal clock signal; and

the plurality of multiplexers provides the second portion of the plurality of data bits to the plurality of output drivers in response to a transition of the second internal clock signal.

24. The memory device of claim 23 wherein the transition of the first internal clock signal occurs between the rising edge transition of the first clock signal and a rising edge transition of a second clock signal.

25. The memory device of claim 24 wherein the transition of the second internal clock signal occurs between the falling edge transition of the first clock signal and a falling edge transition of the second clock signal.

26. The memory device of claim 24 wherein the second clock signal is a delayed version of the first clock signal.

27. The memory device of claim 24 wherein the transition of the first internal clock signal precedes a midpoint between the rising edge transition of the first clock signal and the rising edge transition of the second clock signal by a delay time.

28. The memory device of claim 27 wherein the delay time includes an input receiver delay time.

29. A method of operation of a semiconductor memory device including a memory cell array coupled to a plurality of sense amplifiers, wherein the method of operation of the memory device comprises:

sampling address information synchronously with respect to a first clock signal, wherein the address information includes a row address and a column address, wherein the row address identifies a row of the memory cell array;

sensing data from the row of the memory cell array identified by the row address, wherein the data is sensed by the plurality of sense amplifiers;

accessing, based on the column address, a plurality of data bits of the data sensed by the plurality of sense amplifiers; and

outputting first and second portions of the plurality of data bits, in succession, during a clock cycle of the first clock signal.

30. The method of claim 29 wherein the memory cell array includes a plurality of subarrays, wherein the plurality of data bits is accessed from a first and second subarray of the plurality of subarrays.

31. The method of claim 30 wherein the row address identifies a first row in the first subarray and a first row in the second subarray, wherein the row of the memory cell array includes the first rows in each of the first and second subarrays.

32. The method of claim 31 wherein the row address further identifies a second row in the first subarray and a second row in the second subarray, wherein the row of the memory cell array further includes the second rows in each of the first and second subarrays.

33. The method of claim 29 wherein the address information is sampled during a plurality of clock cycles of the first clock signal.

34. The method of claim 29 wherein the plurality of data bits are output in response to an operation code that specifies a read operation, and wherein the method further includes sampling the operation code synchronously with respect to the first clock signal.

35. The method of claim 34 wherein the operation code includes precharge information to indicate that the plurality of sense amplifiers be precharged after the plurality of data bits are accessed.

36. The method of claim 34 wherein the operation code includes precharge information to indicate that, after the plurality of data bits is accessed, the plurality of sense amplifiers retain the data sensed from the row of the memory cell array.

37. The method of claim 29 further including receiving the first clock signal, wherein the first clock signal is an externally provided periodic signal.

38. The method of claim 37 wherein the outputting of the first and second portions of the plurality of data bits is synchronized with respect to the first clock signal, and wherein the method further includes generating an internal clock signal to synchronize the outputting of the plurality of data bits with respect to the first clock signal, wherein a timing relationship of the internal clock signal with respect to the first clock signal is controlled based on a comparison between the internal clock signal and the first clock signal.

39. The method of claim 38 wherein:

the outputting of the first portion of the plurality of data bits is synchronized with respect to the first clock signal such that the first portion of the plurality of data bits is output midway between the rising edge transition of the first clock signal and a rising edge transition of a second clock signal; and

the outputting of the second portion of the plurality of data bits is synchronized with respect to the first clock signal such that the second portion of the plurality of data bits is output midway between the falling edge transition of the first clock signal and a falling edge transition of the second clock signal.

40. The method of claim 39 wherein the second clock signal is a delayed version of the first clock signal.

41. The method of claim 29 wherein the address information is sampled from an external bus.

42. The method of claim 41 wherein the external bus includes a plurality of signal lines to carry, in a multiplexed format, the plurality of data bits and the address information.

43. A semiconductor memory device, wherein the memory device comprises:

a plurality of subarrays, wherein each subarray of the plurality of subarrays includes a plurality of memory cells;

a plurality of input receivers to sample an operation code synchronously with respect to a first clock signal, wherein the operation code specifies a read operation;

a plurality of sense amplifiers to sense data from a row of the plurality of subarrays, wherein the row is identified by a row address;

a plurality of column decoders, coupled to the plurality of sense amplifiers, to access, based on a column address, a plurality of data bits of the data sensed by the plurality of sense amplifiers; and

a plurality of output drivers to output the plurality of data bits, wherein;

the plurality of output drivers outputs a first portion of the plurality of data bits synchronously with respect to a rising edge transition of the first clock signal; and

the plurality of output drivers outputs a second portion of the plurality of data bits synchronously with respect to a falling edge transition of the first clock signal.

44. The memory device of claim 43 wherein the plurality of subarrays includes first and second subarrays, wherein the plurality of data bits are accessed from at least the first and second subarrays.

45. The memory device of claim 43 wherein the plurality of subarrays includes first and second subarrays, wherein the row address identifies a first row in the first subarray and a first row in the second subarray, wherein the row of the plurality of subarrays includes the first rows in each of the first and second subarrays.

46. The memory device of claim 45 wherein the row address further identifies a second row in the first subarray and a second row in the second subarray, wherein the row of the plurality of subarrays further includes the second rows in each of the first and second subarrays.

47. The memory device of claim 45 wherein:

the first subarray includes a decoder to select, based on the row address, the first row in the first subarray; and

the second subarray includes a decoder to select, based on the row address, the first row in the second subarray.

48. The memory device of claim 43 wherein the plurality of column decoders includes column decoders in each subarray of the plurality of subarrays.

49. The memory device of claim 43 wherein each subarray of the plurality of subarrays includes an array of sense amplifiers that is included in the plurality of sense amplifiers.

50. The memory device of claim 43 further including a plurality of pins, wherein the plurality of output drivers is connected to the plurality of pins, and wherein the plurality of output drivers outputs the plurality of data bits onto an external bus via the plurality of pins.

51. The memory device of claim 50 wherein the plurality of input receivers is connected to a subset of the plurality of pins.

52. The memory device of claim 43 wherein the operation code includes precharge information to indicate, without further instruction, that the plurality of sense amplifiers be precharged after the plurality of data bits is accessed.

53. The memory device of claim 43 wherein the operation code includes precharge information to indicate, without further instruction, that the plurality of sense amplifiers retains the data sensed from the row after the plurality of data bits is accessed.

54. The memory device of claim 43 further including a delay locked loop, coupled to the plurality of output drivers, to synchronize the output of the first and second portions of the plurality of data bits with the first clock signal.

55. The memory device of claim 54 wherein the delay locked loop includes:

a delay line to generate an internal clock signal from the first clock signal, wherein the internal clock signal has a delay with respect to the first clock signal; and

a comparator to compare the internal clock signal with the first clock signal, wherein the delay of the internal clock signal is controlled based on the comparison between the internal clock signal and the first clock signal.

56. The memory device of claim 43 further including a plurality of multiplexers coupled to the plurality of output drivers, wherein the plurality of multiplexers provides the first and second portions of the plural8ity of data bits to the plurality of output drivers;

and

a plurality of internal data lines, coupled to the plurality of sense amplifiers and the plurality of multiplexers, to provide the plurality of data bits to the plurality of multiplexers.

57. The memory device of claim 56 further including a delay locked loop coupled to the plurality of multiplexers, wherein the delay locked loop generates a first internal clock signal and a second internal clock signal, wherein the first and second internal clock signals are complementary, and wherein:

the plurality of multiplexers provides the first portion of the plurality of data bits to the plurality of output drivers in response to a transition of the first internal clock signal; and

the plurality of multiplexers provides the second portion of the plurality of data bits to the plurality of output drivers in response to a transition of the second internal clock signal.

58. The memory device of claim 57 wherein:

the transition of the first internal clock signal occurs midway between the rising edge transition of the first clock signal and a rising edge transition of a second clock signal; and

the transition of the second internal clock signal occurs midway between the falling edge transition of the first clock signal and a falling edge transition of the second clock signal.

59. The memory device of claim 56 wherein the plurality of internal data lines includes an internal data line corresponding to each data bit of the plurality of data bits.