Programmable page table access

• US 6,728,859 B1
• Filed: 07/13/2001
• Issued: 04/27/2004
• Est. Priority Date: 07/13/2001
• Status: Active Grant

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Kissell, Kevin D.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): Namazi, Mehdi
• Application Number:
  US09/905,185
• Time in Patent Office: 1,019 Days
• Field of Search: 711/202-203, 711/207, 711/206
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/652 Page size control

Abstract

An apparatus and method are provided to enable programmable page table accesses in a virtual memory system. The apparatus includes context logic and context configuration logic. The context logic designates an entry within a data structure. The context logic has a plurality of fields, where each of the plurality of fields provides part of a pointer to the entry. The context configuration logic is coupled to the context logic. The context configuration logic prescribes the structure of the each of the plurality of fields. Programming the context configuration logic determines the function by which the context logic derives a useful value from a virtual address associated with an event.

Claims

1. An apparatus in a virtual memory system for providing programmable page table access, the apparatus comprising:

context logic, configured to designate a data structure associated with a block of virtual memory, said context logic comprising a plurality of fields, each of said plurality of fields providing part of a pointer to said data structure; and

context configuration logic, coupled to said context logic, configured to prescribe the structure of said each of said plurality of fields, wherein programming said context configuration logic determines the function by which said context logic derives a useful value from a virtual address associated with an event.

2. The apparatus as recited in claim 1, wherein said plurality of fields comprises:

a first field, for indicating most significant bits of said pointer;

a second field;

coupled to said first field, for indicating more significant bits of said pointer, wherein said more significant bits are less significant than said most significant bits; and

a third field, coupled to said second field, for indicating least significant bits of said pointer, wherein said least significant bits are less significant than said more significant bits.

3. The apparatus as recited in claim 2, wherein said most significant bits designate a base address of said data structure, wherein said base address is provided to said most significant bits via execution of a memory management instruction.

4. The apparatus as recited in claim 3, wherein said more significant bits designate an offset relative to said base address, wherein said offset is provided to said more significant bits by memory management unit logic.

5. The apparatus as recited in claim 4, wherein said offset is provided by memory management logic to indicate upper bits of a virtual address corresponding to an entry.

6. The apparatus as recited in claim 2, wherein the number of said least significant bits correspond to the size of an entry within said data structure.

7. The apparatus as recited in claim 2, wherein said context configuration logic is initialized to prescribe the structure of said each of said plurality of fields in accordance with a legacy memory management protocol.

8. The apparatus as recited in claim 7, wherein programming said context configuration logic after initialization prescribes structure of said each of said plurality of fields in accordance with an extended memory management protocol.

9. The apparatus as recited in claim 8, wherein said context configuration logic is programmed via execution of an instruction from an extended operating system.

10. The apparatus as recited in claim 9, wherein said context logic comprises a first 32-bit register.

11. The apparatus as recited in claim 10, wherein said context configuration logic comprises a second 32-bit register, wherein contiguous asserted bits within said second 32-bit register designate said more significant bits.

42. The method as recited in claim 10, wherein said executing comprises:

asserting contiguous bits within the programmable register to designate the more significant bits.

12. A virtual memory management apparatus for providing programmable page table access, the virtual memory management apparatus comprising:

context logic, configured to designate a data structure associated with a block of virtual memory, said context logic comprising;

a base field, for indicating a base address of said data structure;

an offset field, coupled to said base field, for indicating an offset within said data structure corresponding to an entry within said data structure; and

a zero field, coupled to said offset field, wherein the number of bits within said zero field corresponds to the size of said entry; and

context configuration logic, coupled to said context logic, configured to prescribe the size of said base field, the size of said offset field, and the size of said zero field, wherein the relationship between a virtual address associated with an event and a data structure entry pointer generated by said context logic is specified by programming.

13. The virtual memory management apparatus as recited in claim 12, wherein said offset is provided by memory management logic to indicate upper bits of a virtual address corresponding to said entry.

14. The virtual memory management apparatus as recited in claim 13, wherein contents of said base field are prescribed via execution of an memory management instruction.

15. The virtual memory management apparatus as recited in claim 14, wherein said context configuration logic is initialized to specify the configuration of said data structure in accordance with a legacy memory management protocol.

16. The virtual memory management apparatus as recited in claim 15, wherein programming said context configuration logic after initialization specifies the configuration of said data structure according to an extended memory management protocol.

17. The virtual memory management apparatus as recited in claim 16, wherein said context configuration logic is programmed via execution of an instruction from an extended operating system.

18. The virtual memory management apparatus as recited in claim 13, wherein said context logic comprises a first register, said first register comprising:

most significant bits, for storing said base field;

more significant bits, less significant than said most significant bits within said first register, for storing said offset field; and

least significant bits, less significant that said more significant bits within said first register, for storing said zero field;

wherein concatenation of said most significant bits, said more significant bits, and said least significant bits generates a memory address corresponding to said entry.

19. The virtual memory management apparatus as recited in claim 18, wherein said context configuration logic comprises a second register, wherein contiguous asserted bits within said second register designate said middle bits within said first register.

20. The virtual memory management apparatus as recited in claim 19, wherein said first and second registers comprise 32-bit registers.

21. A computer program product for use with a computing device, the computer program product comprising:

a computer usable medium, having computer readable program code embodied in said medium, for causing an apparatus in a virtual memory system to be described, said apparatus providing programmable page table access, said computer readable program code comprising;

first program code, for describing context logic, said context logic designating an entry within a data structure associated with a block of virtual memory, wherein said context logic comprises a plurality of fields, each of said plurality of fields providing part of a pointer to said entry; and

second program code, coupled to said first program code, for describing context configuration logic, said context configuration logic prescribing the structure of said each of said plurality of fields, wherein programming said context configuration logic determines the function by which said context logic derives a useful value from a virtual address associated with an event.

22. The computer program product as recited in claim 21, wherein said plurality of fields comprises:

a first field, for indicating most significant bits of said pointer;

a second field;

coupled to said first field, for indicating more significant bits of said pointer, wherein said more significant bits are less significant than said most significant bits; and

a third field, coupled to said second field, for indicating least significant bits of said pointer, wherein said least significant bits are less significant than said more significant bits.

23. The computer program product as recited in claim 22, wherein said most significant bits designate a base address of said data structure, wherein said base address is provided to said most significant bits via execution of a memory management instruction.

24. The computer program product as recited in claim 23, wherein said more significant bits designate an offset relative to said base address, wherein said offset is provided to said more significant bits by memory management unit logic.

25. The computer program product as recited in claim 24, wherein said offset is provided by memory management logic to indicate upper bits of said virtual address corresponding to said entry.

26. The computer program product as recited in claim 22, wherein the number of said least significant bits correspond to the size of said entry within said data structure.

27. The computer program product as recited in claim 22, wherein said context configuration logic is initialized to prescribe the structure of said each of said plurality of fields in accordance with a legacy memory management protocol.

28. The computer program product as recited in claim 27, wherein programming said context configuration logic after initialization prescribes structure of said each of said plurality of fields in accordance with an extended memory management protocol.

29. The computer program product as recited in claim 28, wherein said context configuration logic is programmed via execution of an instruction from an extended operating system.

30. The computer program product as recited in claim 29, wherein said context logic comprises a first 32-bit register.

31. The computer program product as recited in claim 30, wherein said context configuration logic comprises a second 32-bit register, wherein contiguous asserted bits within said second 32-bit register designate said more significant bits.

32. A computer data signal embodied in a transmission medium, comprising:

first computer-readable program code, for describing context logic in a virtual memory management apparatus, said context logic designating an entry within a data structure associated with a block of virtual memory, wherein said context logic comprises a plurality of fields, each of said plurality of fields providing part of a pointer to said entry; and

second computer-readable program code, coupled to said first computer-readable program code, for describing context configuration logic, said context configuration logic prescribing the structure of said each of said plurality of fields, wherein programming determines the function by which said context logic derives a useful value from a virtual address associated with an event.

33. The computer data signal as recited in claim 32, wherein said plurality of fields comprises:

a first field, for indicating most significant bits of said pointer;

a second field;

coupled to said first field, for indicating more significant bits of said pointer, wherein said more significant bits are less significant than said most significant bits; and

a third field, coupled to said second field, for indicating least significant bits of said pointer, wherein said least significant bits are less significant than said more significant bits.

34. The computer data signal as recited in claim 33, wherein said most significant bits designate a base address of said data structure, wherein said base address is provided to said most significant bits via execution of a memory management instruction.

35. The computer data signal as recited in claim 34, wherein said more significant bits designate an offset relative to said base address, wherein said offset is provided to said more significant bits by memory management unit logic.

36. The computer data signal as recited in claim 33, wherein said context configuration logic is initialized to prescribe the structure of said each of said plurality of fields in accordance with a legacy memory management protocol.

37. The computer data signal as recited in claim 33, wherein programming said context configuration logic after initialization prescribes structure of said each of said plurality of fields in accordance with an extended memory management protocol.

38. The computer data signal as recited in claim 33, wherein said context configuration logic comprises a 32-bit register, wherein contiguous asserted bits within said 32-bit register designate said more significant bits.

39. A method for providing programmable page table access in a virtual memory management system, the method comprising:

defining the structure of a plurality of pointer parts via a programmable register;

initializing the programmable register such that the structure of the plurality of pointer parts comports with a legacy memory management protocol;

programming the programmable register such that the structure of the plurality of pointer parts comports with an extended memory management protocol; and

generating a pointer to an entry in a data structure by concatenating the plurality of pointer parts.

40. The method as recited in claim 39, wherein said defining comprises:

first specifying a first field, for indicating most significant bits of the pointer;

second specifying a second field;

coupled to the first field, for indicating more significant bits of the pointer, wherein the more significant bits are less significant than the most significant bits; and

third specifying a third field, coupled to the second field, for indicating least significant bits of the pointer, wherein the least significant bits are less significant than the more significant bits.

41. The method as recited in claim 40, wherein said programming comprises:

executing an instruction from an extended operating system.

43. A virtual memory system, for providing programmable virtual memory access, the system comprising:

a central processing unit (CPU), for accessing instructions/data within a physical memory, wherein access of said instructions/data is controlled according to a virtual memory management protocol, said CPU comprising;

context logic, for generating a pointer to a data structure in said physical memory that is associated with a block of virtual memory, said context logic comprising a plurality of fields, each of said plurality of fields providing part of said pointer; and

context configuration logic, coupled to said context logic, for prescribing the structure of said each of said plurality of fields, wherein programming said context configuration logic determines the function by which said context logic derives a useful value from a virtual address associated with an event, where said virtual address is generated by said CPU.