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Processor array and parallel data processing methods

  • US 6,728,862 B1
  • Filed: 05/22/2000
  • Issued: 04/27/2004
  • Est. Priority Date: 05/22/2000
  • Status: Expired due to Term
First Claim
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1. A processor array comprising a plurality of interconnected processor elements, a plurality of instruction buses connected to each of the processor elements at least one data bus connected to each of the processor elements and an instruction selection switch associated with each of the processor elements, each processor element connected to execute instructions from a one of the plurality of instruction buses selected by its instruction selection switch wherein a ratio of the number of processor elements in the processor array to the number of instruction buses in the processor array is greater than 100:

  • 1.

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