Runtime configurable arithmetic and logic cell
DC CAFCFirst Claim
1. A directly addressable configurable unit that can be reconfigured at run time controlled by a primary logic unit (PLU) for processing arithmetic and logic operations (PAE) for use in central processing units (CPUs), multi-processor systems, data flow processors (DFPs), digital signal processors (DSPs), systolic processors and field programmable gate arrays (FPGAs), characterized in thata. a programmable arithmetic and logic unit (EALU) is provided for performing the basic mathematical and logic functions, b. the function and interconnection of the central processor are programmed in directly addressable registers and various data can be processed without reprogramming the PAE, c. there is a state machine (SM UNIT) for controlling the arithmetic and logic unit (EALU), d. registers are provided for each operand (O-REG) and the result (R-REG), some of the registers being designed as shift registers, e. there is feedback of the data of the result register to an input of the EALU over a multiplexer (R2O-MUX), f. a bus unit (BM UNIT) permits pick-up of data from a bus system and feeding the result to a bus system, the bus unit being capable of sending data to multiple receivers and the synchronization of multiple receivers taking place automatically, g. the bus access from the data processing in the EALU is decoupled via the registers and thus each PAE can be regarded as an independent unit, in particular the configuration and reconfiguration of a PAE have no interfering effect on the data transmitters and receivers or on the independent PAEs, h. the sequence of bus transfers is controlled automatically using a state machine (sync UNIT), for which purpose handshake lines oRDY, oACK, rRDY and rACK are available, and i. feedback is sent to the PLU for detection of the processing status and reconfigurability of the PAE (state-back UNIT).
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Abstract
A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a power-saving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers.
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Citations
19 Claims
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1. A directly addressable configurable unit that can be reconfigured at run time controlled by a primary logic unit (PLU) for processing arithmetic and logic operations (PAE) for use in central processing units (CPUs), multi-processor systems, data flow processors (DFPs), digital signal processors (DSPs), systolic processors and field programmable gate arrays (FPGAs), characterized in that
a. a programmable arithmetic and logic unit (EALU) is provided for performing the basic mathematical and logic functions, b. the function and interconnection of the central processor are programmed in directly addressable registers and various data can be processed without reprogramming the PAE, c. there is a state machine (SM UNIT) for controlling the arithmetic and logic unit (EALU), d. registers are provided for each operand (O-REG) and the result (R-REG), some of the registers being designed as shift registers, e. there is feedback of the data of the result register to an input of the EALU over a multiplexer (R2O-MUX), f. a bus unit (BM UNIT) permits pick-up of data from a bus system and feeding the result to a bus system, the bus unit being capable of sending data to multiple receivers and the synchronization of multiple receivers taking place automatically, g. the bus access from the data processing in the EALU is decoupled via the registers and thus each PAE can be regarded as an independent unit, in particular the configuration and reconfiguration of a PAE have no interfering effect on the data transmitters and receivers or on the independent PAEs, h. the sequence of bus transfers is controlled automatically using a state machine (sync UNIT), for which purpose handshake lines oRDY, oACK, rRDY and rACK are available, and i. feedback is sent to the PLU for detection of the processing status and reconfigurability of the PAE (state-back UNIT).
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4. A circuit, comprising:
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a plurality of coarse grained processing array elements;
a primary logic unit communicatively coupled to the processing array elements; and
an internal bus system;
wherein each of the processing array elements is reconfigurable at a run time without effecting other processing array elements and without effecting data streams communicated between transmitters and receivers, by selecting one of a set of predefined, non-alterable instructions according to configuration data sent from the primary logic unit and addressed to the processing array element, and each of the processing array elements is decoupled from the internal bus system. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A reconfigurable data processor comprising:
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a bus; and
coarse grained reconfigurable processing array elements, each one of the processing array elements including;
a bus unit coupling the one of the processing array elements to the bus, input registers storing operands received over the bus via the bus unit from at least one upstream one of the processing array elements at least one configuration register storing configuration data indicating one of a set of predefined, non-alterable instructions, the at least one configuration register receiving the reconfiguration from at least one upstream one of the processing array elements;
a logic circuit performing operations of the operands in accordance with the configuration data, output registers storing result data received from the logic circuit, the result data being transmitted on the bus via the bus unit to at least one downstream one of the processing array elements; and
at least one register coupling the logic circuit to the bus unit.- View Dependent Claims (18, 19)
trigger logic receiving trigger signals over the bus via the bus unit; and
a synchronizer unit connected to the trigger logic, the synchronizer synchronizing operation of the one of the processing array elements as a function of signals received from the trigger logic.
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19. The reconfigurable data processor according to claim 17, wherein each one of the processing array elements further includes:
a multiplexer connected to the logic circuit and the output registers, the multiplexer relaying the result data from the logic circuit to the output registers.
Specification