Method for conserving power in a can microcontroller and a can microcontroller that implements this method

• US 6,728,892 B1
• Filed: 12/30/1999
• Issued: 04/27/2004
• Est. Priority Date: 09/15/1999
• Status: Expired due to Term

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Silvkoff, William J., Birns, Neil E., Habben, Hartmut
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Cao, Chun
• Application Number:
  US09/474,901
• Time in Patent Office: 1,580 Days
• Field of Search: 713/322, 713/320, 713/401, 713/300, 713/201, 713/323, 713/324, 710/15
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: H04L 1/1664 the supervisory signal being transmitted together with payload signals; piggybacking
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/40039 Details regarding the setting of the power status of a node according to activity on the bus
• CPC Class Codes: H04L 12/4135 using bit-wise arbitration
• CPC Class Codes: H04L 12/46 Interconnection of networks
• CPC Class Codes: H04L 2012/40215 Controller Area Network CAN
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 47/621 Individual queue per connection or flow, e.g. per VC
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 67/12 specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method for conserving power in a CAN microcontroller that includes a processor core and a CAN/CAL module that includes a plurality of sub-blocks that cooperatively function to process incoming CAL/CAN messages, which method includes the steps of placing the processor core in a power-reduction mode of operation (e.g., a sleep or idle mode of operation), placing the CAN/CAL module in a power-reduction mode of operation, and activating the CAN/CAL module to process an incoming CAL/CAN message (e.g., to perform automatic hardware assembly of a multi-frame, fragmented CAL/CAN message), thereby terminating the power-reduction mode of operation thereof, while the processor core is in its power-reduction mode of operation. In a preferred embodiment, the CAN/CAL module automatically assembles incoming, multi-frame, fragmented messages while the processor core remains in its power-reduction mode of operation, and the CAN/CAL module generates a message-complete interrupt in response to completion of assembly of the multi-frame, fragmented message, whereby the terminating step is executed in response to the message-complete interrupt. In another embodiment, the method includes the steps of placing the entire CAN microcontroller, including both the processor core and the CAN/CAL module in a power-down mode of operation, detecting receipt of an incoming message, and activating the CAN/CAL module in response to the detecting step to process the incoming message (e.g., to perform automatic hardware assembly of a multi-frame, fragmented CAL/CAN message), thereby terminating the power-down mode of operation of the CAN/CAL module, without terminating the power-down mode of operation of the processor core.

Claims

1. A method for conserving power in a CAN microcontroller, formed by a single integrated circuit (IC), that includes a processor core and a CAN/CAL module that includes a plurality of sub-blocks that cooperatively function to process incoming CAL/CAN messages, the method comprising the steps of:

placing the processor core in a power-reduction mode of operation;

placing the CAN/CAL module in a power-reduction mode of operation; and

,

activating the CAN/CAL module to process an incoming CAL/CAN message, thereby terminating the power-reduction mode of operation thereof, while the processor core is in its power-reduction mode of operations;

wherein the CAN/CAL module is placed in the power-reduction mode of operation only after each respective sub-block of the plurality of sub-blocks of the CAN/CAL module indicates a current inactive state, said processor core indicates a current inactive state, and no incoming CAL/CAN message is detected.

2. The method as set forth in claim 1, wherein the incoming CAL/CAN message is a multi-frame, fragmented CAL/CAN message.

3. The method as set forth in claim 2, further comprising the step of the CAN/CAL module performing automatic hardware assembly of the multi-frame, fragmented CAL/CAN message while the processor core is its power-reduction mode of operation.

4. The method as set forth in claim 3, further comprising the steps of:

generating a message-complete interrupt in response to completion of assembly of the multi-frame, fragmented CAL/CAN message; and

activating the processor core in response to the message-complete interrupt.

5. The method as set forth in claim 1, further comprising repeating the step of placing the CAN/CAL module in a power-reduction mode of operation and activating the CAN/CAL module to process an incoming CAL/CAN message, in seriatim, a plurality of times, while the processor core is in its power reduction mode of operation.

6. The method as set forth in claim 1, wherein the power-reduction mode of operation comprises a sleep state.

7. The method as set forth in claim 1, wherein the power reduction mode of operation comprises an idle mode of operation.

8. The method as set forth in claim 1, wherein the step of placing the processor core in a power reduction mode of operation comprises:

generating a clock disable signal having a first logic level if the processor core has pending interrupts, and having a second logic if the processor core has no pending interrupts; and

disabling a clock applied to the processor core in response to the clock disable signal to thereby place the processor core in the power-reduction mode of operation.

9. A method for conserving power in a CAN microcontroller that includes a processor core and a CAN/CAL module that includes a plurality of sub-blocks that cooperatively function to process incoming CAL/CAN messages, the method comprising the steps of:

placing the processor core in a power-reduction mode of operation;

placing the CAN/CAL module in a power-reduction mode of operation; and

,

activating the CAN/CAL module to process an incoming CAL/CAN message, thereby terminating the power-reduction mode of operation thereof, while the processor core is in its power-reduction mode of operation;

wherein the step of placing the CAN/CAL module in a power-reduction mode operation comprises;

each of the plurality of sub-blocks generating a respective first signal having a first logic level if that sub-block is currently active, and having a second logic level if that sub-block us not currently active;

generating a second signal having a first logic level if any of the first signals are at the first logic level, and having a second logic level in response to all of the first signals having the second logic level;

generating a third signal having a first logic level if the processor core is not idle, and having a second logic level if the processor core is idle;

generating a fourth signal having a first logic level if an incoming message is being received, and having a second logic level if an incoming message is not being received;

generating a clock disable signal in response to the second, third, and fourth signals all being at their respective second logic level; and

disabling a clock applied to the CAN/CAL module in response to the clock disable signal to thereby place the CAN/CAL module in the power-reduction mode of operation.

10. A method for conserving power in a CAN microcontroller that includes a processor core and a CAN/CAL module that includes a plurality of sub-blocks that cooperatively function to process incoming CAL/CAN messages, the method comprising the steps of:

placing the processor core in a power-reduction mode of operation;

placing the CAN/CAL module in a power-reduction mode of operation; and

,

activating the CAN/CAL module to process an incoming CAL/CAN message, thereby terminating the power-reduction mode of operation thereof, while the processor core is in its power-reduction mode of operation;

wherein the step of placing the CAN/CAL module in a power reduction mode operation comprises;

each of the plurality of sub-blocks generating a respective first signal having a first logic level if that sub-block is currently active, and having a second logic level if that sub-block is not currently active;

generating a second signal having a first logic level if any of the first signals are at the first logic level, and having a second logic level in response to all of the first signals having the second logic level;

generating a third signal having a first logic level if the processor core has pending interrupts, and having a second logic level if the processor core has no pending interrupts;

generating a fourth signal having a first logic level if an incoming message is being received, and having a second logic level if an incoming message is not being received;

generating a clock disable signal in response to the second, third, and fourth signals all being at their respective second logic level; and

disabling a clock applied to the CAN/CAL module in response to the clock disable signal to thereby place the CAN/CAL module in the power-reduction mode of operation.

11. The method as set forth in claim 10, further comprising the step of activating the processor core in response to an interrupt.

12. A method for conserving power in a CAN microcontroller, formed by a single integrated circuit (IC), that includes a processor core and a CAN/CAL module, the method comprising the steps of:

placing the processor core in a power-reduction mode of operation while the CAN/CAL module is actively processing an incoming CAL/CAN message; and

,

terminating the power-reduction mode of operation in response to an interrupt;

wherein the CAN/CAL module automatically assembles incoming, multi-frame, fragmented messages while the processor core remains in its power-reduction mode of operation; and

further comprising the step of;

placing the CAN/CAL module in a power-reduction mode of operation only after confirming that each respective sub-block of a plurality of sub-blocks of the CAN/CAL module indicates a current inactive state, said processor core indicates a current inactive state, and no incoming CAL/CAN message is detected.

13. The method as set forth in claim 12, wherein the power-reduction mode of operation comprises a sleep state.

14. The method as set forth in claim 12, wherein the power-reduction mode of operation comprises an idle mode of operation.

15. The method as set forth in claim 12, wherein the CAN/CAL module generates a message-complete interrupt in response to completion of assembly of the multi-frame, fragmented message, whereby the terminating step is executed in response to the message-complete interrupt.

16. The method as set forth in claim 12, wherein the step of placing the processor core in a power-reduction mode of operation comprises:

generating a clock disable signal having a first logic level if the processor core has pending interrupts, and having a second logic level if the processor core has no pending interrupts; and

disabling a clock applied to the processor core in response to the clock disable signal to thereby place the processor core in the power-reduction mode of operation.

17. A method for conserving power in a CAN microcontroller, formed by a single integrated circuit (IC), that includes a processor core and a CAN/CAL module, the method comprising the steps of:

placing the entire CAN microcontroller, including both the processor core and the CAN/CAL module in a power-down mode of operation only after detecting that each respective sub-block of the plurality of sub-blocks of the CAN/CAL module indicates a current inactive state, said processor core indicates a current inactive state, and no incoming CAL/CAN message is detected;

detecting receipt of an incoming message; and

,

activating the CAN/CAL module in response to the detecting step to process the incoming message, thereby terminating the power-down mode of operation of the CAN/CAL module, without terminating the power-down mode of operation of the processor core.

18. The method as set forth in claim 17, further comprising the step of placing the processor core in a power reduction mode of operation in response to the detecting step, wherein:

the processor core can be substantially instantaneously woken up when in the power-down mode of operation; and

the processor core can be woken up over a prescribed wake-up period when in the power-down mode of operation.

19. The method as set forth in claim 17, wherein the placing step comprises:

determining whether the CAN/CAL module is ready to be placed into the power-down mode of operation; and

stopping a main system clock in response to a determination that the CAN/CAL module is ready to be placed into the power-down mode of operation.

20. The method as set forth in claim 18, wherein the CAN/CL module automatically assembles incoming, multi-frame, fragmented messages while the processor core remains in its power-reduction mode of operation.

21. The method as set forth in claim 17, further comprising the step of terminating the power-down mode of operation of the entire CAN microcontroller, including both the processor core and the CAN/CAL module, in response to an external interrupt.

22. The method as set forth in claim 18, further comprising the step of terminating the power-down mode of operation of the entire CAN microcontroller, including both the processor core and the CAN/CAL module, in response to system reset command.

23. A CAN microcontroller, formed by a single integrated circuit (IC), comprising:

a processor core that runs CAN applications;

a CAN/CAL module that includes a plurality of sub-blocks that cooperatively function to process incoming CAL/CAN messages, the CAN/CAL module including a power control module that includes;

means for placing the processor core in a power-reduction mode of operation;

means for placing the CAN/CAL module in a power-reduction mode of operation; and

,

means for activating the CAN/CAL module to process an incoming CAL/CAN message, thereby terminating the power-reduction mode of operation thereof, while the processor core is in its power-reduction mode of operation;

wherein

the CAN/CAL module is placed in the power-reduction mode of operation only after each respective sub-block of the plurality of sub-blocks of the CAN/CAL module indicates a current inactive state, said processor core indicates a current inactive state, and no incoming CAL/CAN message is detected.

24. The CAN microcontroller as set forth in claim 23, wherein the incoming CAL/CAN message is a multi-frame, fragmented CAL/CAN message.

25. The CAN microcontroller as set forth in claim 24, wherein the CAN/CAL module is operable to perform automatic hardware assembly of the multi-frame, fragmented CAL/CAN message while the processor core is in its power-reduction mode of operation.

26. The CAN microcontroller as set forth in claim 25, wherein the power control module further includes:

means for generating a message-complete interrupt in response to completion of assembly of the multi-frame, fragmented CAL/CAN message; and

means for activating the processor core in response to the message-complete interrupt.

27. The CAN microcontroller as set forth in claim 23, wherein the power-reduction mode of operation comprises a sleep state.

28. The CAN microcontroller as set forth in claim 23, wherein the power-reduction mode of operation comprises an idle mode of operation.

29. The CAN microcontroller as set forth in claim 23, wherein the means for placing the CAN/CAL module in a power-reduction mode operation comprises:

means for generating a clock disable signal having a first logic level if the processor core has pending interrupts, and having a second logic level if the processor core has no pending interrupts; and

means for disabling a clock applied to the processor core in response to the clock disable signal to thereby place the processor core in the power-reduction mode of operation.

30. A CAN microcontroller, formed by a single integrated circuit (IC), comprising:

a processor core that runs CAN applications;

a CAN/CAL module that includes a plurality of sub-blocks that cooperatively function to process incoming CAL/CAN messages, the CAN/CAL module including a power control module that includes;

means for placing the processor core in a power-reduction mode of operation;

means for placing the CAN/CAL module in a power-reduction mode of operation; and

,

means for activating the CAN/CAL module to process an incoming CAL/CAN message, thereby terminating the power-reduction mode of operation thereof, while the processor core is in its power-reduction mode of operation;

wherein the means for placing the CAN/CAL module in a power-reduction mode operation comprises;

means associated with each of the plurality of sub-blocks for generating a respective first signal having a first logic level if that sub-block is currently active, and having a second logic level if that sub-block is not currently active;

means for generating a second signal having a first logic level if any of the first signals are at the first logic level, and having a second logic level in response to all of the first signals having the second logic level;

means for generating a third signal having a first logic level if the processor core is not idle, and having a second logic level if the processor core is idle;

means for generating a fourth signal having a first logic level if an incoming message is being received, and having a second logic level if an incoming message is not being received;

means for generating a clock disable signal in response to the second, third, and fourth signals all being at their respective second logic level; and

means for disabling a clock applied to the CAN/CAL module in response to the clock disable signal to thereby place the CAN/CAL module in the power-reduction mode of operation.

31. A CAN microcontroller, formed by a single integrated circuit (IC) comprising:

a processor core that runs CAN applications;

a CAN/CAL module that includes a plurality of sub-blocks that cooperatively function to process incoming CAL/CAN messages, the CAN/CAL module including a power control module that includes;

means for placing the processor core in a power-reduction mode of operation;

means for placing the CAN/CAL module in a power-reduction mode of operation; and

,

means for activating the CAN/CAL module to process an incoming CAL/CAN message, thereby terminating the power-reduction mode of operation thereof, while the processor core is in its power-reduction mode of operation;

wherein the means for placing the CAN/CAL module in a power-reduction mode operation comprises;

means associated with each of the plurality of sub-blocks for generating a respective first signal having a first logic level if that sub-block is currently active, and having a second logic level if that sub-block is not currently active;

means for generating a second signal having a first logic level if any of the first signals are at the first logic level, and having a second logic level in response to all of the first signals having the second logic level;

means for generating a third signal having a first logic level if the processor core has pending interrupts, and having a second logic level if the processor core has no pending interrupts;

means for generating a fourth signal having a first logic level if an incoming message is being received, and having a second logic level if an incoming message is not being received;

means for generating a clock disable signal in response to the second, third and fourth signals all being at their respective second logic level; and

means for disabling a clock applied to the CAN/CAL module in response to the clock disable signal to thereby place the CAN/CAL module in the power-reduction mode of operation.

32. A CAN microcontroller, formed by a single integrated circuit (IC), comprising:

a processor core that runs CAN applications;

a CAN/CAL module that processes incoming CAL/CAN messages, the CAN/CAL module including a power control module that includes;

means for placing the processor core in a power-reduction mode of operation while the CAN/CAL module is actively processing an incoming CAL/CAN message; and

,

means for terminating the power-reduction mode of operation of said processor core in response to an interrupt; and

means for placing the CAN/CAL module in a power-reduction mode, each respective sub-block of a plurality of sub-blocks of the CAN/CAL module indicates a current inactive state, said processor core indicates a current inactive state, and no incoming CAL/CAN message is detected.

33. The CAN microcontroller as set forth in claim 32, wherein the CAN/CAL module automatically assembles incoming, multi-frame, fragmented messages while the processor core remains in its power-reduction mode of operation.

34. The CAN microcontroller as set forth in claim 33, wherein the CAN/CAL module generates the interrupt in response to completion of assembly of the multi-frame, fragmented CAL/CAN message.

35. The CAN microcontroller as set forth in claim 32, wherein the means for placing the processor core in a power-reduction mode of operation comprises:

means for generating a clock disable signal having a first logic level if the processor core has pending interrupts, and having a second logic level if the processor core has no pending interrupts; and

means for disabling a clock applied to the processor core in response to the clock disable signal to thereby place the processor core in the power reduction mode of operation.

36. A CAN microcontroller, formed by a single integrated circuit (IC), comprising:

a processor core that runs CAN applications;

a CAN/CAL module that processes incoming CAL/CAN messages, the CAN/CAL module including a power control module that includes;

means for placing the entire CAN microcontroller, including both the processor core and the CAN/CAL module in a power-down mode of operation;

means for detecting receipt of an incoming message; and

,

means for activating the CAN/CAL module in response to detection of the receipt of an incoming message, to process the incoming message, thereby terminating the power-down mode of operation of the CAN/CAL module, without terminating the power-down mode of operation of the processor core;

wherein the means for placing CAN microcontroller in a power-down mode of operation includes means for determining that each respective sub-block of a plurality of sub-blocks of the CAN/CAL module indicates a current inactive state, said processor core indicates a current inactive state, and no incoming CAL/CAN message is detected before the CAN/CAL module is placed in the power-reduction mode of operation.

37. The CAN microcontroller as set forth in claim 36, wherein the power control module further includes means for placing the processor core in a power-reduction mode of operation in response to detection of the receipt of an incoming message, wherein:

the processor core can be substantially instantaneously woken up when in the power-down mode of operation; and

the processor core can be woken up over a prescribed wake-up period when in the power-down mode of operation.

38. The CAN microcontroller as set forth in claim 36, wherein the means for placing comprises:

means for determining whether the CAN/CAL module is ready to be placed into the power-down mode of operation; and

means for stopping a main system clock in response to a determination that the CAN/CAL module is ready to be placed into the power-down mode of operation.

39. The CAN microcontroller as set forth in claim 37, wherein the CAN/CAL module automatically assembles incoming, multi-frame, fragmented messages while the processor core remains in its power-reduction mode of operation.

40. The CAN microcontroller as set forth in claim 36, wherein the power control module further includes means for terminating the power-down mode of operation of the entire CAN microcontroller, including both the processor core and the CAN/CAL module, in response to an external interrupt.

41. The CAN microcontroller as set forth in claim 36, wherein the power control module further includes means for terminating the power-down mode of operation of the entire CAN microcontroller, including both the processor core and the CAN/CAL module, in response to a system reset command.

42. A CAN microcontroller, formed by a single integrated circuit (IC), comprising:

a processor core that runs CAN applications;

a CAN/CAL module that includes a plurality of sub-blocks that cooperatively function to process incoming CAL/CAN messages, the CAN/CAL module including a power control module that includes;

first logic circuitry that places the processor core in a power-reduction mode of operation;

second logic circuitry that places the CAN/CAL module in a power-reduction mode of operation; and

,

third logic circuitry that activates the CAN/CAL module to process an incoming CAL/CAN message, thereby terminating the power-reduction mode of operation thereof, while the processor core is in its power-reduction mode of operation;

wherein the second logic circuitry places the CAN/CAL module in a power reduction mode of operation only after determining each respective sub-block of a plurality of sub-blocks of the CAN/CAL module indicates a current inactive state, said processor core indicates a current inactive state, and no incoming CAL/CAN message is detected.

43. A CAN microcontroller, formed by a single integrated circuit (IC), comprising:

a processor core that runs CAN applications;

a CAN/CAL module that processes incoming CAL/CAN messages, the CAN/CAL module including a power control module that includes;

first logic circuitry that places the processor core in a power-reduction mode of operation while the CAN/CAL module is actively processing an incoming CAL/CAN message, wherein the first logic circuitry places the CAN/CAL module in a power reduction mode of operation only after determining that each respective sub-block of a plurality of sub-blocks of the CAN/CAL module indicates a current inactive state, said processor core indicates a current inactive state, and no incoming CAL/CAN message is detected subsequent to the active processing of a current CAL/CAN message; and

,

second logic circuitry that terminates the power-reduction mode of operation in response to an interrupt.

44. A CAN microcontroller, formed by a single integrated circuit (IC), comprising:

a processor core that runs CAN applications;

a CAN/CAL module that processes incoming CAL/CAN messages, the CAN/CAL module including a power control module that includes;

first logic circuitry that places the entire CAN microcontroller, including both the processor core and the CAN/CAL module in a power-down mode of operation;

second logic circuitry that detects receipt of an incoming message; and

,

third logic circuitry that activates the CAN/CAL module in response to detection of the receipt of an incoming message, to process the incoming message, thereby terminating the power-down mode of operation of the CAN/CAL module, without terminating the power-down mode of operation of the processor core;

wherein the first logic circuitry places the CAN/CAL module in a power reduction mode of operation only after determining that each respective sub-block of a plurality of sub-blocks of the CAN/CAL module indicates a current inactive state, said processor core indicates a current inactive state, and no incoming CAL/CAN message is detected.