Microcomputer with test instruction memory
First Claim
Patent Images
1. A microcomputer comprisingan instruction execution unit;
- a test circuit for enabling the microcomputer to operate in a normal state or in a test state alternatively;
an instruction memory interface enabled in the normal state to apply instruction information to the instruction execution unit from instruction memory addresses sequenced under control of program flow;
a test sequencing unit enabled in the test state to control application of instruction information to the instruction execution unit, the test sequencing unit overruling sequencing as applied in the normal state, so that a same source of an instruction is used cyclically to apply a same instruction information from the same source to the instruction execution unit repeatedly, independent any sequencing implied by the instruction information, wherein said test sequencing unit measures current consumed when it executes the instruction under test.
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Abstract
The microcomputer has an instruction memory interface that applies instructions to an instruction execution unit. In a normal state instructions are obtained from instruction memory under control of a normal program counter. In a test state a same source of an instruction is used cyclically to apply a same instruction information from a test instruction memory. Normal addressing is suppressed in the test state, so that the same instruction is executed repeatedly independent of normal program flow.
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Citations
15 Claims
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1. A microcomputer comprising
an instruction execution unit; -
a test circuit for enabling the microcomputer to operate in a normal state or in a test state alternatively;
an instruction memory interface enabled in the normal state to apply instruction information to the instruction execution unit from instruction memory addresses sequenced under control of program flow;
a test sequencing unit enabled in the test state to control application of instruction information to the instruction execution unit, the test sequencing unit overruling sequencing as applied in the normal state, so that a same source of an instruction is used cyclically to apply a same instruction information from the same source to the instruction execution unit repeatedly, independent any sequencing implied by the instruction information, wherein said test sequencing unit measures current consumed when it executes the instruction under test. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A microcomputer comprising
an instruction execution unit; -
a test circuit for enabling the microcomputer to operate in a normal state or in a test state alternatively;
an instruction memory interface enabled in the normal state to apply instruction information to the instruction execution unit from instruction memory addresses sequenced under control of program flow;
a test sequencing unit enabled in the test state to control application of instruction information to the instruction execution unit, the test sequencing unit overruling sequencing as applied in the normal state, so that a same source of an instruction is used cyclically to apply a same instruction information from the same source to the instruction execution unit repeatedly, independent of any sequencing implied by the instruction information, the microprocessor comprising test instruction storage and a test instruction counter for cyclically counting selection signals selecting the test instruction information from the test instruction information wherein the instruction execution unit being arranged to operate asychronously, the microcomputer adapting an instruction execution frequency to a response time of the instruction execution unit. - View Dependent Claims (8, 9, 10)
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11. A microcomputer comprising
an instruction execution unit; -
a test circuit for enabling the microcomputer to operate in a normal state or in a test state alternatively;
an instruction memory interface enabled in the normal state to apply instruction information to the instruction execution unit from instruction memory addresses sequenced under control of program flow;
a test sequencing unit enabled in the test state to control application of instruction information to the instruction execution unit, the test sequencing unit overruling sequencing as applied in the normal state, so that a same source of an instruction is used cyclical to apply a same instruction information from the same source to the instruction execution unit repeatedly, independent of many sequencing implied by the instruction information, the microprocessor comprising test instruction storage and a test instruction counter for cyclically counting selection signals selecting the test instruction information from the test instruction storage; and
a test instruction circuit counting selectably three or four locations in test instruction storage before being reset. - View Dependent Claims (12, 13, 14)
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15. A method of testing a microcomputer, the method comprising supplying an instruction under test repeatedly to an instruction execution unit from a test instruction storage that is selected bypassing a program counter based instruction addressing mechanism used during operation of the microcomputer outside testing;
arranging the instruction execution unit to operate asynchronously, the microcomputer adapting an instruction execution frequency to a response time of the instruction execution unit.
Specification