Microcomputer with test instruction memory

• US 6,728,900 B1
• Filed: 09/07/2000
• Issued: 04/27/2004
• Est. Priority Date: 09/10/1999
• Status: Expired due to Fees

• Current Assignee: DSP Group Switzerland AG (Synaptics Incorporated)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Meli, Louis Marcel
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): PUENTE, EMERSON C
• Application Number:
  US09/656,833
• Time in Patent Office: 1,328 Days
• Field of Search: 714/17, 714/25, 714/47, 714/30, 712/227, 717/127-130, 702/58, 702/64
• US Class Current: 714/25
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 2201/88 Monitoring involving counting

Abstract

The microcomputer has an instruction memory interface that applies instructions to an instruction execution unit. In a normal state instructions are obtained from instruction memory under control of a normal program counter. In a test state a same source of an instruction is used cyclically to apply a same instruction information from a test instruction memory. Normal addressing is suppressed in the test state, so that the same instruction is executed repeatedly independent of normal program flow.

Claims

1. A microcomputer comprising

an instruction execution unit;

a test circuit for enabling the microcomputer to operate in a normal state or in a test state alternatively;

an instruction memory interface enabled in the normal state to apply instruction information to the instruction execution unit from instruction memory addresses sequenced under control of program flow;

a test sequencing unit enabled in the test state to control application of instruction information to the instruction execution unit, the test sequencing unit overruling sequencing as applied in the normal state, so that a same source of an instruction is used cyclically to apply a same instruction information from the same source to the instruction execution unit repeatedly, independent any sequencing implied by the instruction information, wherein said test sequencing unit measures current consumed when it executes the instruction under test.

2. A microcomputer according to claim 1, the microcomputer comprising test instruction storage and a test instruction counter for cyclically counting selection signals selecting the instruction information from the test instruction storage, wherein a given supply voltage is applied to the instruction execution unit for determining a time of duration when said instruction execution unit executes an instruction under test.

3. A microcomputer according to claim 2, further comprising a test instruction reset circuit for resetting the test instruction counter to its initial value when the test instruction counter has reached a selectable value.

4. A microcomputer according to claim 2, the test instruction storage having a size not bigger than needed for storing a longest instruction executable by the instruction execution unit.

5. A Microcomputer according to claim 2, wherein the instruction storage comprises a plurality of registers, for storing successive units of an instruction under test, the test instruction counter counting successive units of the instruction under test, the test sequencing unit supplying the units to the instruction unit successively.

6. A microcomputer according to claim 2, wherein the instruction storage comprises a plurality of registers, for storing successive units of an instruction under test, the registers being part of a test scan chain.

7. A microcomputer comprising

an instruction execution unit;

a test circuit for enabling the microcomputer to operate in a normal state or in a test state alternatively;

an instruction memory interface enabled in the normal state to apply instruction information to the instruction execution unit from instruction memory addresses sequenced under control of program flow;

a test sequencing unit enabled in the test state to control application of instruction information to the instruction execution unit, the test sequencing unit overruling sequencing as applied in the normal state, so that a same source of an instruction is used cyclically to apply a same instruction information from the same source to the instruction execution unit repeatedly, independent of any sequencing implied by the instruction information,

the microprocessor comprising test instruction storage and a test instruction counter for cyclically counting selection signals selecting the test instruction information from the test instruction information wherein the instruction execution unit being arranged to operate asychronously, the microcomputer adapting an instruction execution frequency to a response time of the instruction execution unit.

8. A microcomputer according to claim 7, comprising a test instruction reset circuit for resetting the test instruction counter to its initial value when the test instruction counter has reached a selectable value.

9. A microcomputer according to claim 7, the instruction storage comprising a plurality of registers, for storing successive units of an instruction under test, the test instruction counter counting successive units of the instruction under test, the test sequencing unit supplying the units to the instruction unit successively.

10. A microprocessor according to claim 7, the instruction storage comprising a plurality of registers, for storing successive units of an instruction under test, the registers being part of a test scan chain.

11. A microcomputer comprising

an instruction execution unit;

a test circuit for enabling the microcomputer to operate in a normal state or in a test state alternatively;

an instruction memory interface enabled in the normal state to apply instruction information to the instruction execution unit from instruction memory addresses sequenced under control of program flow;

a test sequencing unit enabled in the test state to control application of instruction information to the instruction execution unit, the test sequencing unit overruling sequencing as applied in the normal state, so that a same source of an instruction is used cyclical to apply a same instruction information from the same source to the instruction execution unit repeatedly, independent of many sequencing implied by the instruction information,

the microprocessor comprising test instruction storage and a test instruction counter for cyclically counting selection signals selecting the test instruction information from the test instruction storage; and

a test instruction circuit counting selectably three or four locations in test instruction storage before being reset.

12. A microcomputer according to claim 11, comprising a test instruction reset circuit for resetting the test instruction counter to its initial value when the test instruction counter has reached a selectable value.

13. A microcomputer according to claim 11, the instruction storage comprising a plurality of registers, for storing successive units of an instruction under test, the test instruction counter counting successive units of the instruction under test, the test sequencing unit supplying the units to the instruction unit successively.

14. A microcomputer according to claim 11, the instruction storage comprising a plurality of registers, for storing successive units of an instruction under test, the registers being part of a test scan chain.

15. A method of testing a microcomputer, the method comprising supplying an instruction under test repeatedly to an instruction execution unit from a test instruction storage that is selected bypassing a program counter based instruction addressing mechanism used during operation of the microcomputer outside testing;

arranging the instruction execution unit to operate asynchronously, the microcomputer adapting an instruction execution frequency to a response time of the instruction execution unit.