Integrated circuit having a self-test device for carrying out a self-test of the integrated circuit

• US 6,728,902 B2
• Filed: 01/23/2001
• Issued: 04/27/2004
• Est. Priority Date: 07/23/1998
• Status: Expired due to Term

• Current Assignee: ChangXin Memory Technologies, Inc.
• Original Assignee: Infineon Technologies AG
• Inventors: Kaiser, Robert, Schamberger, Florian
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): DUNCAN, MARC M
• Application Number:
  US09/767,393
• Publication Number:
  US 20010011904A1
• Time in Patent Office: 1,190 Days
• Field of Search: 714/30, 714/733, 714/724, 714/27, 714/32, 714/25, 702/183, 701/31
• US Class Current: 714/30
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G06F 11/2635 using a storage for the test inputs, e.g. test ROM, script files

Abstract

An integrated circuit includes a self-test device which is provided for executing a self-test of the integrated circuit and which has a control output. A program memory is connected to the self-test device for storing at least one test program supplied from outside the integrated circuit. The test program is run by the self-test device during execution of a self-test. The self-test device controls loading of a respective test program to be run into the program memory from outside the integrated circuit through the control output thereof.

Claims

1. In an integrated circuit, the improvement comprising:

a self-test device for carrying out a self-test of the integrated circuit, said self-test device having a control output; and

a program memory connected to said self-test device for storing at least one test program supplied from outside the integrated circuit and executed while said self-test device carries out a self-test;

said self-test device using said control output to control loading of a respective test program to be executed, from outside the integrated circuit into said program memory.

2. The integrated circuit according to claim 1, wherein said self-test device executes a plurality of the test programs in succession and, after completion of a preceding test program, automatically loads a respective next test program into said program memory from outside the integrated circuit, by control through said control output.

3. The integrated circuit according to claim 2, wherein said self-test device has a result signal output through which a common result signal for tests having been carried out in accordance with the executed test programs is supplied outside the integrated circuit after execution of a plurality of test programs having been loaded in succession into said program memory from outside the integrated circuit.