IC with shared scan cells selectively connected in scan path
First Claim
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1. An integrated circuit comprising:
- A. a first circuit having data input leads connected to the inputs of input data buffers, each input data buffer being subject to damage when all data input signals on a data input lead are placed in a high impedance state, the first circuit also having control output leads connected to the outputs of output control buffers;
B. a second circuit having first data output leads coupled to respective data input leads of the first circuit and having a first control input lead coupled to a control output lead of the first circuit, the first data output leads being connected to the outputs of data output tri-state buffers, each tri-state buffer having a tri-state control input for, when active, placing the output of the tri-state buffer in a high impedance output state, the first control input lead being connected to the input of a control input buffer, the output of the control input buffer being coupled to the tri-state control inputs of the tri-state buffers, the output of each tri-state buffer being subject to damage upon the output, when active, being driven to a logic level data output signal in contention with another driven logic level data output signal occurring at its data output lead;
C. a third circuit having second data output leads also coupled to respective data input leads of the first circuit and having a second control input lead coupled to a control output lead of the first circuit, the second data output leads being connected to the outputs of data output tri-state buffers, each tri-state buffer having a tri-state control input for, when active, placing the output of the tri-state buffer in a high impedance output state, the second control input lead being connected to the input of a control input buffer, the output of the control input buffer being coupled to the tri-state control inputs of the tri-state buffers, the output of each tri-state buffer being subject to damage upon the output, when active, being driven to a logic level data output signal in contention with another driven logic level data output signal occurring at its data output lead; and
F. a serial scan path passing through the first, second, and third circuits, the scan path having an scan input coupled to a serial test data input lead supplying test data and having an scan output coupled to a serial test data output lead retrieving test data, the scan path including dedicated scan cells and shared scan cells with one scan cell being coupled in series with one input buffer and one scan cell being coupled in series with one output buffer, each dedicated scan cell including two memories for shifting test data on the scan path without interfering with normal operation of the first, second, and third circuits, each shared scan cell including one memory that is shared for normal and test operation of the first, second, and third circuits and shifting test data on the scan path through the shared scan cell interferes with normal operation of the first, second, and third circuits, the dedicated scan cells being always connected in the serial scan path and the shared scan cells being selectively connected in the serial scan path.
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Abstract
This patent describes a boundary scan system where memories, i.e. flip flops or latches, used in data scan cells are also used functionally, but memories used in control scan cells are dedicated for test and not used functionally. The control scan cells can be scanned while the circuit is in functional mode, since their memories are dedicated. However, the data scan cells can only be scanned after the circuit transitions into test mode, since their memories are shared. This boundary scan system advantageously provides; (1) lower test circuitry overhead since the data scan cells use shared memories, (2) safe entry into test mode since the control scan cells can be scanned during functional mode to pre-load safe control conditions, and (3) avoidance of floating (i.e. 3-state) busses that can cause high current situations.
362 Citations
4 Claims
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1. An integrated circuit comprising:
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A. a first circuit having data input leads connected to the inputs of input data buffers, each input data buffer being subject to damage when all data input signals on a data input lead are placed in a high impedance state, the first circuit also having control output leads connected to the outputs of output control buffers;
B. a second circuit having first data output leads coupled to respective data input leads of the first circuit and having a first control input lead coupled to a control output lead of the first circuit, the first data output leads being connected to the outputs of data output tri-state buffers, each tri-state buffer having a tri-state control input for, when active, placing the output of the tri-state buffer in a high impedance output state, the first control input lead being connected to the input of a control input buffer, the output of the control input buffer being coupled to the tri-state control inputs of the tri-state buffers, the output of each tri-state buffer being subject to damage upon the output, when active, being driven to a logic level data output signal in contention with another driven logic level data output signal occurring at its data output lead;
C. a third circuit having second data output leads also coupled to respective data input leads of the first circuit and having a second control input lead coupled to a control output lead of the first circuit, the second data output leads being connected to the outputs of data output tri-state buffers, each tri-state buffer having a tri-state control input for, when active, placing the output of the tri-state buffer in a high impedance output state, the second control input lead being connected to the input of a control input buffer, the output of the control input buffer being coupled to the tri-state control inputs of the tri-state buffers, the output of each tri-state buffer being subject to damage upon the output, when active, being driven to a logic level data output signal in contention with another driven logic level data output signal occurring at its data output lead; and
F. a serial scan path passing through the first, second, and third circuits, the scan path having an scan input coupled to a serial test data input lead supplying test data and having an scan output coupled to a serial test data output lead retrieving test data, the scan path including dedicated scan cells and shared scan cells with one scan cell being coupled in series with one input buffer and one scan cell being coupled in series with one output buffer, each dedicated scan cell including two memories for shifting test data on the scan path without interfering with normal operation of the first, second, and third circuits, each shared scan cell including one memory that is shared for normal and test operation of the first, second, and third circuits and shifting test data on the scan path through the shared scan cell interferes with normal operation of the first, second, and third circuits, the dedicated scan cells being always connected in the serial scan path and the shared scan cells being selectively connected in the serial scan path. - View Dependent Claims (2, 3, 4)
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Specification
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Current AssigneeTexas Instruments, Inc.
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Original AssigneeTexas Instruments, Inc.
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InventorsWhetsel, Lee D.
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Primary Examiner(s)Decady, Albert
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Assistant Examiner(s)Torres, Joseph D.
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Application NumberUS09/758,089Publication NumberTime in Patent Office1,203 DaysField of Search714/726, 714/727, 714/729, 714/730US Class Current714/727CPC Class CodesG01R 31/318536 Scan chain arrangements, e....
