Clock distribution networks and conductive lines in semiconductor integrated circuits

• US 6,730,540 B2
• Filed: 04/18/2002
• Issued: 05/04/2004
• Est. Priority Date: 04/18/2002
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Tru-Si Technologies, Inc.
• Inventors: Siniaguine, Oleg
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Le, Thao X.
• Application Number:
  US10/127,144
• Publication Number:
  US 20030199123A1
• Time in Patent Office: 747 Days
• Field of Search: 327/295, 327/296, 327/297, 327/298, 327/299, 257/690, 257/698, 257/723, 257/777, 438/107, 438/108, 438/110
• US Class Current: 438/107
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A clock distribution network (110) is formed on a semiconductor interposer (320) which is a semiconductor integrated circuit. An input terminal (120) of the clock distribution network is formed on one side of the interposer, and output terminals (130) of the clock distribution network are formed on the opposite side of the interposer. The interposer has a through hole (360), and the clock distribution network includes a conductive feature going through the through hole. The side of the interposer which has the output terminals (130) is bonded to a second integrated circuit (310) containing circuitry clocked by the clock distribution network. The other side of the interposer is bonded to a third integrated circuit or a wiring substrate (330). The interposer contains a ground structure, or ground structures (390, 510), that shield circuitry from the clock distribution network. Conductive lines (150) in an integrated circuit are formed in trenches (610) in a semiconductor substrate.

Claims

1. A manufacturing method comprising manufacturing a first semiconductor integrated circuit comprising a first side and a second side that are opposite to each other, the first semiconductor integrated circuit comprising a first semiconductor substrate, wherein the first semiconductor integrated circuit comprises a clock distribution network comprising:

an input contact pad on the second side of the first semiconductor integrated circuit, the input contact pad being bondable to circuitry external to the first semiconductor integrated circuit;

a plurality of output contact pads on the first side, the output contact pads being bondable to circuitry external to the first semiconductor integrated circuit; and

clock paths from the input contact pad to the output contact pads, wherein at least one of the clock paths passes through the first semiconductor substrate, entering the first semiconductor substrate on the second side to lead a clock signal out of the first semiconductor substrate on the first side to circuitry bondable to the output contact pads and external to the first semiconductor integrated circuit;

wherein the first semiconductor substrate comprises a through hole passing between the first and second sides, and the clock path passing through the first semiconductor substrate passes through a conductive feature formed in the through hole;

wherein the conductive feature is a metal feature insulated from the first semiconductor substrate;

wherein the manufacture of the first integrated circuit comprises;

forming an opening in the first side of the first semiconductor substrate at a location of the through hole, the opening not going through the first semiconductor substrate;

forming the conductive feature in the opening; and

thinning the first semiconductor integrated circuit on the second side to expose the conductive feature on the second side.

2. The method of claim 1 wherein the conductive feature extends to the input contact pad.

3. The method of claim 1 wherein:

the first semiconductor substrate farther comprises one or more additional through holes passing between the first and second sides; and

the first semiconductor integrated circuit further comprises;

one or more additional contact pads on the second side at each of the additional through holes;

a conductive feature in each of the additional through holes to provide at least a portion of a path for a signal and/or a power voltage and/or a ground voltage between the corresponding additional contact pad and a circuit element on the first side.

4. The method of claim 3 wherein for at least one of the additional through holes, the corresponding circuit element on the first side is a contact pad bondable to circuitry external to the first semiconductor integrated circuit.

5. The method of claim 4 wherein for said at least one additional through hole, the corresponding circuit element on the first side is located over the respective through hole, and the entire electrical path connecting the circuit element on the first side to the respective additional contact pad on the second side forms an angle with at least one of surfaces of the first semiconductor integrated circuit on the first and second sides or with at least one of the first semiconductor substrate'"'"'s surfaces on the first and second sides.

6. The method of claim 1 further comprising forming in the first semiconductor integrated circuit a conductive structure to be held at a constant voltage, wherein at least a portion of the clock distribution network is located between the conductive structure and the first semiconductor substrate.

7. The method of claim 6 wherein the conductive structure comprises a conductive plane or a conductive grid.

8. The method of claim 1 further comprising forming in the first semiconductor integrated circuit a conductive structure to be held at a constant voltage, wherein at least a portion of the clock distribution network is separated from the first semiconductor substrate by the conductive structure.

9. The method of claim 8 wherein the conductive structure comprises a conductive plane or a conductive grid.

10. The method of claim 1 wherein the clock path passing through the first semiconductor substrate comprises a transistor having an active area in the first semiconductor substrate.

11. A method comprising:

providing a clock signal to an input contact pad of a clock distribution network formed in a first semiconductor integrated circuit;

the clock distribution network coupling the clock signal to output contact pads, wherein the output contact pads are located on a first side of the first semiconductor integrated circuit and the input contact pad is located on a second side of the first semiconductor integrated circuit, the second side being opposite to the first side;

wherein the output contact pads are bonded to contact pads of a second semiconductor integrated circuit; and

wherein the clock signal is coupled to the output contact pads via clock paths from the input contact pad to the output contact pads, wherein at least one of the clock paths passes through the first semiconductor substrate, entering the first semiconductor substrate on the second side to lead a clock signal out of the first semiconductor substrate on the first side to the second semiconductor integrated circuit;

wherein the first semiconductor integrated circuit comprises a first conductive structure between at least a portion of the clock distribution network and the second integrated circuit, and the first conductive structure is held at a constant voltage during operation of the first semiconductor integrated circuit;

wherein the first semiconductor integrated circuit is bonded to a third circuit which is a wiring substrate and/or a semiconductor integrated circuit, wherein one or more contact pads of the third circuit are bonded to one or more contact pads of the first semiconductor integrated circuit which are located on the second side of the first semiconductor integrated circuit;

wherein the first semiconductor integrated circuit comprises a second conductive structure held at a constant voltage, wherein the second conductive structure is located between at least a portion of the clock distribution network and the third circuit.

12. The method of claim 11 wherein the first semiconductor substrate comprises an opening in the first side and also comprises a conductive feature formed in the opening and insulated from the first semiconductor substrate;

and

wherein the clock path passing through the first semiconductor substrate passes through the conductive feature.

13. The method of claim 11 wherein the first conductive structure comprises a conductive plane or a conductive grid.

14. The method of claim 11 wherein the second conductive structure comprises a conductive plane or a conductive grid.

15. The method of claim 11 wherein the clock distribution network is a part of a larger clock distribution network, and the larger clock distribution network has another part located in the second semiconductor integrated circuit.

16. A manufacturing method comprising manufacturing a structure comprising a first semiconductor integrated circuit bonded to a second semiconductor integrated circuit;

wherein the first semiconductor integrated circuit comprises;

a first side and a second side that are opposite to each other;

a semiconductor substrate; and

a clock distribution network comprising;

an input contact pad on the second side of the first semiconductor integrated circuit, the input contact pad being bondable to circuitry external to the first semiconductor integrated circuit; and

a plurality of output contact pads on the first side, the output contact pads being bonded to the second semiconductor integrated circuit;

wherein the second semiconductor integrated circuit comprises a plurality of contact pads positioned at a first surface of the second semiconductor integrated circuit; and

the method comprises bonding the contact pads of the second semiconductor integrated circuit to respective output contact pads of the clock distribution network to provide a plurality of clock paths from the input contact pad through the output contact pads to the second semiconductor integrated circuit, wherein at least one of the clock paths passes through the first semiconductor substrate, entering the first semiconductor substrate on the second side and exiting the first semiconductor substrate on the first side to enter the second semiconductor integrated circuit from the first side of the first semiconductor integrated circuit;

wherein the first semiconductor substrate comprises an opening in the first side and also comprises a conductive feature formed in the opening; and

the method comprises, after the bonding operation, thinning the first semiconductor integrated circuit on the second side to expose the conductive feature on the second side;

wherein the clock path passing through the first semiconductor substrate passes through the conductive feature.

17. The method of claim 16 wherein the first semiconductor integrated circuit is part of a semiconductor wafer, and the method further comprises, after the thinning operation, dicing the semiconductor wafer to obtain a die comprising the first semiconductor integrated circuit.

18. A manufacturing method comprising manufacturing a structure comprising a first semiconductor integrated circuit bonded to a second semiconductor integrated circuit;

wherein the first semiconductor integrated circuit comprises;

a first side and a second side that are opposite to each other;

a semiconductor substrate; and

a clock distribution network comprising;

an input contact pad on the second side of the first semiconductor integrated circuit, the input contact pad being bondable to circuitry external to the first semiconductor integrated circuit; and

a plurality of output contact pads on the first side, the output contact pads being bonded to the second semiconductor integrated circuit;

wherein the second semiconductor integrated circuit comprises a plurality of contact pads positioned at a first surface of the second semiconductor integrated circuit; and

the method comprises bonding the contact pads of the second semiconductor integrated circuit to respective output contact pads of the clock distribution network to provide a plurality of clock paths from the input contact pad through the output contact pads to the second semiconductor integrated circuit, wherein at least one of the clock paths passes through the first semiconductor substrate, entering the first semiconductor substrate on the second side and exiting the first semiconductor substrate on the first side to enter the second semiconductor integrated circuit from the first side of the first semiconductor integrated circuit;

wherein the first integrated circuit comprises a first conductive structure between at least a portion of the clock distribution network and the second integrated circuit, and the first conductive structure is held at a constant voltage during operation of the apparatus;

wherein the method further comprises bonding the first semiconductor integrated circuit to a third circuit which is a wiring substrate and/or a semiconductor integrated circuit, wherein the bonding operation comprises bonding one or more contact cads of the third circuit to one or more contact pads of the first semiconductor integrated circuit which are located on the second side of the first semiconductor integrated circuit;

wherein the first semiconductor integrated circuit comprises a second conductive structure to be held at a constant voltage, wherein the second conductive structure is located between at least a portion of the clock distribution network and the third circuit.

19. The method of claim 18 wherein the first conductive structure comprises a conductive plane or a conductive grid.

20. The method of claim 18 wherein the second conductive structure comprises a conductive plane or a conductive grid.

21. The method of claim 18 wherein the clock distribution network is a part of a larger clock distribution network, and the larger clock distribution network has another part located in the second semiconductor integrated circuit.