Method of forming SiGe gate electrode

• US 6,730,588 B1
• Filed: 12/20/2001
• Issued: 05/04/2004
• Est. Priority Date: 12/20/2001
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Schinella, Richard
• Primary Examiner(s): GUERRERO, MARIA F
• Application Number:
  US10/026,407
• Time in Patent Office: 866 Days
• Field of Search: 438/622, 438/652, 438/655, 438/657, 438/666, 438/669, 438/672, 438/682, 438/933, 438/585, 438/592, 438/598, 257/412, 257/413
• US Class Current: 438/592
• CPC Class Codes: H01L 21/2807 the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

The present invention provides a method of forming SiGe gate electrodes using a thin nucleation layer. A dielectric layer is formed on a semiconductor wafer and a thin silicon nucleation layer deposited on top of the dielectric layer. A SiGe conducting film is deposited on the patterned silicon layer. The ratio of germanium to silicon in the gaseous source mixture for the silicon and germanium layer is selected so that the SiGe conducting film deposits on the nucleation layer but fails to deposit on the dielectric.

Claims

1. A method of forming a gate electrode on a semiconductor device, the method comprising:

forming a dielectric layer on a semiconductor wafer;

depositing a thin silicon layer having a thickness in the range of 100 to 500 Angstroms on the dielectric layer;

patterning and etching the thin silicon layer to form a silicon nucleation layer and to expose portions of the dielectric layer;

forming a self-aligned gate electrode by depositing a silicon germanium conducting film on the silicon nucleation layer using a material which selectively deposits on the nucleation layer and which fails to deposit on the exposed portions of the dielectric layer; and

depositing a metal layer on the deposited silicon germanium conducting film.

2. The method recited in claim 1 wherein the metal layer is one of titanium and cobalt.

3. The method recited in claim 1 further comprising annealing the metal layer to form a germanide silicide contact.

4. The method recited in claim 1 wherein the silicon layer comprises at least one of amorphous silicon and polycrystalline silicon.

5. The method recited in claim 1 wherein the dielectric layer comprises silicon dioxide (SiO₂).

6. The method recited in claim 1 wherein the silicon germanium conducting film is deposited at a temperature in the range from about 300 to 800 degrees C.

7. The method recited in claim 1 wherein the metal layer is formed in situ during the formation of the silicon germanium film.

8. The method recited in claim 1 wherein the silicon germanium conducting film is deposited using a gaseous mixture comprising germane and at least one of silane (SiH₄) and dichlorosilane (SiH₂Cl₂).

9. The method recited in claim 1 wherein the patterning and etching of the silicon layer comprises depositing a photoresist layer on the silicon layer.

10. The method recited in claim 8 wherein the proportions of germane and at least one of silane and dichlorosilane (SiH₂Cl₂) are selected to preclude deposition of SiGe on the dielectric layer.

11. The method recited in claim 8 wherein the selective depositing of the silicon germanium conducting film is performed by adjusting the ratio of germane to dichlorosilane (SiH₂Cl₂) in the gaseous mixture to about 1:

5.

12. The method recited in claim 8 wherein the ratio of germane to dichlorosilane (SiH₂Cl₂) is in the range from about 0.025 to 1.00.

13. The method recited in claim 9 wherein the photoresist layer ranges from about 100 Angstroms to 2000 Angstroms in thickness.

14. The method recited in claim 8 wherein the gaseous mixture further comprises dopants for doping the silicon germanium conducting film.

15. The method recited in claim 14 wherein the dopants are maintained at a constant concentration during the deposition of the silicon germanium conducting film.

16. The method recited in claim 14 wherein the dopant concentration is changed during the deposition of the silicon germanium conducting film to provide a doping gradient in the silicon germanium conducting film.

17. A method of forming a gate electrode on a semiconductor device, the method comprising:

forming a dielectric layer on a semiconductor wafer;

depositing a silicon layer having a thickness in the range of 100 to 500 Angstroms on the dielectric layer;

patterning and etching the silicon layer to form a gate electrode nucleation layer; and

forming a gate electrode by depositing a silicon germanium conducting film on the gate electrode nucleation layer using a material which selectively deposits on the nucleation layer and which fails to deposit on the dielectric layer.

18. A method of forming a gate electrode on a semiconductor device, the method comprising:

forming a dielectric layer on a semiconductor wafer;

depositing a silicon layer on the dielectric layer;

patterning and etching the silicon layer to form a gate electrode nucleation layer; and

forming a gate electrode by depositing a silicon germanium conducting film on the gate electrode nucleation layer using a gaseous mixture comprising germane and at least one of silane (SiH₄) and dichlorosilane (SiH₂Cl₂) which selectively deposits on the nucleation layer and which fails to deposit on the dielectric layer,

wherein the gaseous mixture further comprises dopants for doping the silicon layer and the dopant concentration is changed during the deposition of the silicon germanium conducting film to provide a doping gradient in the silicon germanium conducting film.