Whole chip ESD protection
First Claim
1. A whole chip electrostatic discharge, ECD, first embodiment circuit comprising:
- a PN diode whose p-side connects to the input/output, I/O pad to be protected and whose N-side is connected to Vcc supply voltage, a PMOS FET plus NMOS FET 2-device input stage connected between Vcc and Vss, a resistor plus NMOS FET first mid stage connected between Vcc and Vss (ground), a resistor to ground second mid-stage, and a PMOS FET plus NMOS FET output stage connected between Vcc and Vss (ground) whose input connects from the mid stages and whose output drives an unused I/O pad.
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Accused Products
Abstract
This invention provides two circuit embodiments for a whole chip electrostatic discharge, ESD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.
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Citations
12 Claims
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1. A whole chip electrostatic discharge, ECD, first embodiment circuit comprising:
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a PN diode whose p-side connects to the input/output, I/O pad to be protected and whose N-side is connected to Vcc supply voltage, a PMOS FET plus NMOS FET 2-device input stage connected between Vcc and Vss, a resistor plus NMOS FET first mid stage connected between Vcc and Vss (ground), a resistor to ground second mid-stage, and a PMOS FET plus NMOS FET output stage connected between Vcc and Vss (ground) whose input connects from the mid stages and whose output drives an unused I/O pad. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification