Highly configurable capacitive transducer interface circuit

• US 6,731,121 B1
• Filed: 08/19/2002
• Issued: 05/04/2004
• Est. Priority Date: 10/15/1999
• Status: Expired due to Term

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Microsensors Incorporated
• Inventors: Hsu, Ying, Su, Kirk, Saunders, Christ
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): KERVEROS, JAMES C
• Application Number:
  US10/110,889
• Time in Patent Office: 624 Days
• Field of Search: 324/658, 324/660, 324/661, 324/676, 324/678, 324/672, 324/669, 324/684, 324/686, 324/690, 324/662, 340/870.37
• US Class Current: 324/678
• CPC Class Codes: G01D 5/24 by varying capacitance

Abstract

A transducer interface circuit (10) for use with a capacitive sensor (20). The interface circuit (10), provided on application specific IC, includes numerous trims and adjustments that permit it to operate with a differential, balanced-pair sensors (20A) or a singled-ended sensor (2013). In particular, the circuit (10) provides a capacitive adjustment section (100) and a capacitive trans-impedance amplifier section (200) that are configured with capacitor adjustment controls (110) and gain adjustment controls (210) that, along with other controls, are provided as control registers. The capacitive trans-impedance amplifier section (300) periodically reverses the voltages across the sensor (20), and the capacitive adjustment section (200), after blanking a feedback capacitance (CF) that is used to integrate excess charge caused by a difference in capacitance. A low pass filter section 300 provides bandwidth adjustment without requiring any external components. An output buffer section (400) includes further trim controls for gain and offset, is also governed by an offset selection bit SOFF that adjusts the output range to be optimally suited for the balanced-pair sensors (20A) or a singled-ended sensor (20B).

Claims

1. A capacitive transducer interface circuit that produces an output value that is proportional to a change in capacitance of a sense capacitor in a capacitive transducer comprising:

an integrated circuit having;

(1) a capacitive adjustment section that is electrically connected to the sense capacitor, including;

(a) a capacitor array circuit;

(b) means for configuring the capacitance of the capacitor array circuit and for combining the capacitance of the capacitor array circuit with the capacitance of the sense capacitor to provide a substantially null value when the capacitive transducer is in a null position; and

(2) a capacitive trans-impedance amplifier section that is electrically connected to the sense capacitor and the capacitive adjustment section, including;

(a) a trans-impedance amplifier means for producing an output signal that is proportional to the change in capacitance of the sense capacitor; and

(b) means for configuring the gain of the capacitive trans-impedance amplifier to provide a desired dynamic range.

2. The capacitive transducer interface circuit of claim 1 wherein the means for configuring the capacitance comprises:

a register that stores a capacitance configuration value; and

means for modifying the capacitance of the capacitor array circuit in accordance with the capacitance configuration value.

3. The capacitive transducer interface circuit of claim 2 wherein the capacitor array circuit is a binary weighted array of parallel capacitors.

4. The capacitive transducer interface circuit of claim 1 wherein the capacitive trans-impedance amplifier comprises:

an amplifier circuit having an inverting input, a non-inverting input, and an output;

wherein the gain of the capacitive trans-impedance amplifier is determined by a feedback capacitance connected between the output and the non-inverting input.

5. The capacitive transducer interface circuit of claim 4 wherein the means for configuring the gain of the capacitive trans-impedance amplifier comprises:

a register that stores a gain configuration value; and

means for modifying the feedback capacitance in accordance with the configuration value.

6. The capacitive transducer interface circuit of claim 1 further comprising:

a low pass filter section that modifies the output signal in accordance with a characteristic bandwidth; and

means for configuring the characteristic bandwidth of the low pass filter section.

7. The capacitive transducer interface circuit of claim 6 further comprising:

an output buffer section that provides a desired output impedance, including;

an amplifier circuit that provides additional gain and a desired DC offset;

means for configuring the additional gain; and

means for configuring the desired DC offset.

8. The capacitive transducer interface circuit of claim 1 wherein the capacitive adjustment section is configurable to operate with:

(1) a differential-type capacitive transducer that is defined by a common plate and a pair of outer plates to provide a balanced-pair of first and second sense capacitors that are connected in series to provide an upper sensor terminal, a lower sensor terminal, and a common sensor terminal;

or

(2) a singled ended-type capacitive transducer that is defined by one pair of plates to provide a single sense capacitor having first and second sensor terminals.

9. The capacitive transducer interface circuit of claim 8 wherein the capacitor array circuit is a first capacitor array circuit, wherein the means for configuring the capacitance of the first capacitor array circuit is a first means for configuring;

and wherein the capacitive adjustment section further comprises;

a second capacitor array circuit; and

a second means for configuring the capacitance of the second capacitor array circuit,

the second capacitor array circuit being connected in series with the first capacitor array circuit to provide an upper capacitive array terminal, a lower capacitive array terminal, and a common capacitive array terminal.

10. The capacitive transducer interface circuit of claim 9 wherein the capacitive adjustment section is configured to operate with the differential-type capacitive transducer by connecting the upper sensor terminal, the lower sensor terminal, and the common sensor terminal to the upper capacitive array terminal, the lower capacitive array terminal, and the common capacitive array terminal, respectively, to form a capacitive divider circuit with the first sense capacitor and the first capacitive array circuit in parallel with one another in a top portion thereof and the second sense capacitor and the second capacitive array circuit in parallel with one another in a bottom portion thereof.

11. The capacitive transducer interface circuit of claim 9 wherein the capacitive adjustment section is configured to operate with the singled ended-type capacitive transducer by connecting the first sensor terminal to the common capacitive array terminal and connecting the second sensor terminal to the lower capacitive array terminal to form a capacitive divider circuit with the first capacitive array circuit in a top portion thereof and the single sense capacitor and the second capacitive array circuit in parallel with one another in a bottom portion thereof.

12. A capacitive transducer interface circuit that produces an output value that is proportional to a difference in capacitance between first and second capacitors that are connected together at a common terminal, comprising:

(a) a trans-impedance amplifier means for producing an output signal that is proportional to the difference in capacitance between the first and second capacitors, said trans-impedance amplifier means including an operational amplifier having an inverting input, a non-inverting input, and an output, with the inverting input connected to the common terminal, with the non-inverting input connected to a reference ground, and with a feedback capacitance connected between the output and the non-inverting input;

(b) a means for repeatedly (1) discharging the feedback capacitance, (2) applying a voltage difference across the first capacitors to charge the first capacitor while applying an equal potential voltage across the second capacitor to discharge the second capacitor; and

(3) then reversing the voltages applied to the first and second capacitors such that the first capacitor discharges into the second capacitor and integrates charge into or out of the feedback capacitance to the extent there is any difference in capacitance between the first and second capacitors.