TFI probe I/O wrap test method

• US 6,731,128 B2
• Filed: 01/04/2002
• Issued: 05/04/2004
• Est. Priority Date: 07/13/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Das, Gobinda, Motika, Franco
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US10/035,186
• Publication Number:
  US 20020058346A1
• Time in Patent Office: 851 Days
• Field of Search: 324/754, 324/760, 324/761, 324/765, 324/537, 324/538, 714/726, 714/727, 438/14, 438/17
• US Class Current: 324/750.05
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49764 with testing or indicating

Abstract

A structure for testing external connections to semiconductor devices. The structure includes an external electrical path between selected external connections on the semiconductor devices.

Claims

1. A method for testing external C4 connections to digital semiconductor devices at the wafer level, the method comprising:

providing an external electrical path via a thin film interposer probe between a selected subset of external C4 connections on the digital semiconductor devices; and

carrying out the testing by sending at least one signal through the external electrical path,

wherein the testing comprises at least one of a boundary scan and an input/output wrap test.

2. The method according to claim 1, further comprising:

pairing all adjacent input/output pairs.

3. The method according to claim 1, wherein the test comprises a high frequency closed loop self test of drivers and receivers.

4. The method according to claim 1, wherein the test comprises burn-in.

5. The method according to claim 1, further comprising:

interfacing a driver from an input/output to a receiver of a corresponding paired input/output.

6. The method according to claim 1, wherein providing the external electrical path comprises:

providing a thin film of electrically insulating material;

providing a plurality of passages through the thin fun of electrically insulating material, wherein the passages are arranged in a pattern corresponding to a pattern of external connections on the semiconductor device;

providing electrically conducting material arranged in the plurality of passages; and

providing electrical connections between the electrically conducting material arranged in the plurality of passages.

7. The method according to claim 6, further comprising:

providing a space transformer connected to the electrically conducting material arranged in the plurality of passages.

8. The method according to claim 1, wherein the external electrical path is provided between pain of external connections on the semiconductor devices.

9. The method according to claim 1, wherein the external electrical path is provided between a plurality of external connections on the semiconductor devices.

10. The method according to claim 1, wherein the external electrical path is provided between non-adjacent external connections on the semiconductor devices.