Method and apparatus for reducing PLL lock time

• US 6,731,146 B1
• Filed: 05/09/2000
• Issued: 05/04/2004
• Est. Priority Date: 05/09/2000
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Gallardo, Keith
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): COX, CASSANDRA F
• Application Number:
  US09/567,802
• Time in Patent Office: 1,456 Days
• Field of Search: 327/147, 327/149, 327/156, 327/158, 327/145, 327/105, 327/45
• US Class Current: 327/158
• CPC Class Codes: H03L 2207/08 Modifications of the phase-locked loop for ensuring constant frequency when the power supply fails or is interrupted, e.g. for saving power
• CPC Class Codes: H03L 2207/18 Temporarily disabling, deactivating or stopping the frequency counter or divider
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/14 for assuring constant frequency when supply or correction voltages fail or are interrupted
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

The lock time is reduced in a phase locked loop frequency synthesizer that has both active modes and standby modes. In the active mode the frequency synthesizer operates to maintain a stable frequency output. The standby or sleep mode is used to reduce power consumption when the frequency synthesizer is not required to provide a frequency output. When the synthesizer is placed in standby mode the most recent value of the Voltage Controlled Oscillator (VCO) tuning voltage is maintained on the VCO tuning control line of the frequency synthesizer. The voltage is maintained on the VCO tuning output pin in Integrated Circuit (IC) frequency synthesizers. The voltage error on the VCO tuning pin is minimized thereby minimizing the lock time of the frequency synthesizer.

Claims

1. A method for reducing the lock time of a Phase Locked Loop (PLL) comprising:

sampling a Voltage Controlled Oscillator (VCO) control voltage of an active PLL;

maintaining the VCO control voltage at the sampled VCO control voltage in response to a command signal, wherein the command signal is a sleep signal,

maintaining power to a memory element during a period when the sleep signal is active;

storing a ratio of a reference divider in the memory element when the sleep signal is active; and

restoring the ratio to the reference divider from the memory element when the sleep signal is no longer active.

2. The method of claim 1 further comprising planting the PLL in a low power mode.

3. The method of claim 2 wherein the task of placing the PLL in the low power mode occurs in response to the command signal.

4. A frequency synthesizer Integrated Circuit (IC) comprising:

a control signal output; and

a voltage hold circuit;

wherein the voltage hold circuit samples the control signal output when the frequency synthesizer IC is in an active mode and maintains the control signal output when the frequency synthesizer IC is in a low power mode in response to a command signal, wherein;

the command signal is a sleep signal,

the frequency synthesizer IC switches from the active mode the low power mode in response to a command signal, wherein the command signal is a sleep signal,

the frequency synthesizer IC maintains power to a memory element during a period when the sleep signal is active,

the frequency synthesizer IC stores a ratio of a reference divider in the memory element when the sleep signal is active; and

the frequency synthesizer IC restores the ratio to the reference divider from the memory element when the sleep signal is no longer active.

5. The frequency synthesizer IC of claim 4 wherein the control signal output is a Voltage Controlled Oscillator (VCO) control signal output.