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Method and apparatus for reducing PLL lock time

  • US 6,731,146 B1
  • Filed: 05/09/2000
  • Issued: 05/04/2004
  • Est. Priority Date: 05/09/2000
  • Status: Expired due to Fees
First Claim
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1. A method for reducing the lock time of a Phase Locked Loop (PLL) comprising:

  • sampling a Voltage Controlled Oscillator (VCO) control voltage of an active PLL;

    maintaining the VCO control voltage at the sampled VCO control voltage in response to a command signal, wherein the command signal is a sleep signal, maintaining power to a memory element during a period when the sleep signal is active;

    storing a ratio of a reference divider in the memory element when the sleep signal is active; and

    restoring the ratio to the reference divider from the memory element when the sleep signal is no longer active.

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