Track and hold with dual pump circuit

• US 6,731,155 B2
• Filed: 12/03/2002
• Issued: 05/04/2004
• Est. Priority Date: 02/13/2002
• Status: Expired due to Fees

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Sanchez, Mario, Chen, Hsin-Shu, Song, Bang-Sup, Hakkarainen, J. Mikko, Bacrania, Kantilal, Sung, Eric C.
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US10/308,775
• Publication Number:
  US 20030151430A1
• Time in Patent Office: 518 Days
• Field of Search: 327/91, 327/93, 327/94, 327/95, 327/96, 327/390, 327/536, 327/589
• US Class Current: 327/390
• CPC Class Codes: H03M 1/165 in which two or more residues with respect to different reference levels in a stage are used as input signals for the next stage, i.e. multi-residue type
• CPC Class Codes: H03M 1/365 the voltage divider being a single resistor string

Abstract

A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS—VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.

Claims

1. A dual pump circuit having an input and an output, comprising:

a transmission gate including a p-channel transistor and an n-channel transistor, each transistor having a control terminal and a pair of current terminals coupled between the dual pump input and the dual pump output; and

a dual charge pump including first and second pump circuits, each coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors and operative to linearize operation of the corresponding transmission gate transistor.

2. The dual pump circuit of claim 1, wherein the p-channel transistor is a PMOS transistor, wherein the first pump circuit comprises a PMOS charge pump circuit coupled to drive a gate of the PMOS transistor, wherein the n-channel transistor is an NMOS transistor, and wherein the second pump circuit comprises an NMOS charge pump circuit coupled to drive a gate of the NMOS transistor.

3. The dual pump circuit of claim 2, wherein the first and second pump circuits are each operative to maintain gate to source voltage minus threshold voltage of a corresponding transmission gate transistor constant for a varying signal at the dual pump input.

4. The dual pump circuit of claim 2, wherein the PMOS and NMOS transistors are approximately equal in size.

5. The dual pump circuit of claim 2, wherein the PMOS and NMOS transistors each have approximately the same conductance.

6. The dual pump circuit of claim 1, wherein each of the first and second pump circuits comprise:

a source follower circuit coupled to the dual pump input; and

a switched capacitor circuit, coupled to the source follower circuit and to the control terminal of the corresponding transmission gate transistor, that combines input voltage with a change in threshold voltage and that controls the control terminal of the corresponding transmission gate transistor based on the combined voltage.

7. The dual pump circuit of claim 6, wherein the source follower circuit comprises:

an operational amplifier having a non-inverting input coupled to the dual pump input, an inverting input and an output;

a MOS transistor having a control terminal coupled to the output of the differential amplifier and a pair of current terminals coupled between a supply voltage and the inverting input of the differential amplifier; and

a constant current bias coupled to the inverting input of the differential amplifier.

8. The dual pump circuit of claim 7, wherein a gamma parameter of the MOS transistor and a corresponding one of the transmission gate transistors is approximately equal to provide threshold voltage compensation.

9. The dual pump circuit of claim 7, wherein the switched capacitor circuit comprises:

a capacitor; and

first and second switches coupled on either end of the capacitor, that charge the capacitor with a common mode voltage in a first position and that couple the capacitor between the output of the differential amplifier and the control terminal of the corresponding transmission gate transistor in a second position.

10. The dual pump circuit of claim 9, wherein the switched capacitor circuit further includes a switch that couples the control terminal of the corresponding transmission gate transistor to the common mode voltage while the switched capacitor circuit capacitor is being charged.

11. A track and hold circuit for sampling an input signal, comprising:

at least one sampling capacitor;

at least one dual pump sampling circuit, each comprising;

a transmission gate including a p-channel transistor and an n-channel transistor, each transistor having a control terminal and a pair of current terminals coupled between the input signal and a pump output; and

a dual charge pump including first and second pump circuits, each having an input coupled to receive the input signal, an output coupled to a control terminal of a corresponding one of the p-channel and n-channel transistors, and an activation input, and each configured to linearize operation of a corresponding one of the transmission gate transistors; and

a sample control circuit coupled to activation inputs of each of the at least one dual pump sampling circuit and to each sampling capacitor, the sample control circuit operative to set common-mode voltage on each sampling capacitor, to activate the dual pump sampling circuit to sample the input signal via each sampling capacitor, and then to deactivate each dual pump sampling circuit to provide a sampled output signal.

12. The track and hold circuit of claim 11, wherein each of the first and second pump circuits of each dual charge pump comprises:

a source follower circuit coupled to receive the input signal; and

a switched capacitor circuit, coupled to the source follower circuit and to the control terminal of a corresponding one of the transmission gate transistors, that combines an input voltage level with a threshold voltage differential and that controls the control terminal of the corresponding transmission gate transistor based on the combined voltage.

13. The track and hold circuit of claim 12, further comprising:

the source follower circuit comprising;

a operational amplifier having a non-inverting input coupled to receive the input signal, an inverting input and an output;

a metal oxide semiconductor (MOS) transistor having a control terminal coupled to the output of the operational amplifier and a pair of current terminals coupled between a supply voltage and the inverting input of the operational amplifier; and

a current sink coupled to the inverting input of the operational amplifier; and

the switched capacitor circuit comprising;

a capacitor; and

first and second switches coupled on either side of the capacitor and controlled by an activation input, that charges the capacitor with a common mode voltage in a deactivated position and that couples the capacitor between the output of the operational amplifier and the control terminal of a corresponding transmission gate transistor in an activated position.

14. The track and hold circuit of claim 13, wherein the p-channel and n-channel transistors of the transmission gate comprise PMOS and NMOS transistors, respectively, and wherein a gamma parameter of the source follower circuit MOS transistor and a corresponding one of the transmission gate transistors is approximately equal.

15. The track and hold circuit of claim 11, the input signal comprising a differential input signal with positive and negative polarities, further comprising:

the at least one dual pump sampling circuit including a first dual pump sampling circuit coupled to sample the positive polarity of the input signal and a second dual pump sampling circuit coupled to sample the negative polarity of the input signal;

the at least one sampling capacitor comprising a first sampling capacitor having a first end coupled to a pump output of the first dual pump sampling circuit and a second sampling capacitor having a first end coupled to a pump output of the second dual pump sampling circuit; and

the sample control circuit comprising;

a differential amplifier having an inverting input coupled to a second side of the first sampling capacitor, a non-inverting input coupled to a second side of the second sampling capacitor, and an output;

a feedback circuit including a first resistive switch coupled between the first end of the first sampling capacitor and the differential amplifier output and a second resistive switch coupled between the first end of the second sampling capacitor and the differential amplifier output; and

a control circuit, coupled to the first and second dual pump sampling circuits and the feedback circuit, that operates in a periodic manner by activating the first and second dual pump sampling circuits and deactivating the feedback circuit during a first portion of each cycle and then by deactivating the first and second dual pump sampling circuits and activating the feedback circuit during a second portion of each cycle.

16. The track and hold circuit of claim 15, wherein the differential amplifier is fully differential having an inverting output and a non-inverting output, the amplifier control circuit further comprising:

an input common mode circuit, coupled to the control circuit, including a switched input common mode voltage circuit coupled between the inverting and non-inverting inputs of the differential amplifier and activated by the control circuit during activation of the first and second dual pump sampling circuits; and

an output common mode circuit, coupled to the control circuit, including a switched output common mode voltage circuit coupled between the inverting and non-inverting outputs of the differential amplifier and activated by the control circuit during activation of the input common mode circuit.

17. A track and hold circuit, comprising:

an differential amplifier having a differential input and a differential output;

a common mode input circuit coupled to the differential input of the differential amplifier;

a common mode output circuit coupled to the differential output of the differential amplifier;

a first sampling capacitor having a first end coupled to a first input polarity of the differential amplifier and a second end;

a second sampling capacitor having a first end coupled to a second input polarity of the differential amplifier and a second end;

a first feedback resistive device coupled between the second end of the first sampling capacitor and a first output polarity of the differential amplifier;

a second feedback resistive device coupled between the second end of the second sampling capacitor and a second output polarity of the differential amplifier;

a pair of dual pump circuits, each dual pump circuit having an input for sampling a corresponding polarity of a differential input signal and an output coupled to a second input of a corresponding one of the first and second sampling capacitors, each comprising;

a transmission gate including a p-channel device and an n-channel device, the p-channel device having a control terminal and a pair of current terminals coupled between a corresponding polarity of the differential input signal and the second input of the corresponding sampling capacitor and the n-channel device having a control terminal and a pair of current terminals coupled between a corresponding polarity of the differential input signal and the second input of the corresponding sampling capacitor;

an n-channel pump circuit having an input coupled to the corresponding polarity of the differential input signal and an output coupled to the control terminal of the n-channel device; and

a p-channel pump circuit having an input coupled to the corresponding polarity of the differential input signal and an output coupled to the control terminal of the p-channel device.

18. The track and hold circuit of claim 17, wherein the p-channel and n-channel devices of each dual pump circuit comprise metal oxide semiconductor (MOS) transistors.

19. The track and hold circuit of claim 17, wherein the first and second feedback resistive devices each comprise:

a p-channel transistor having a control terminal and a pair of current terminals coupled between the second input of a corresponding one of the first and second sampling capacitors and a corresponding one of the first and second output polarities of the differential amplifier; and

an n-channel device having a control terminal and a pair of current terminals coupled between the second input of a corresponding one of the first and second sampling capacitors and a corresponding one of the first and second output polarities of the differential amplifier.

20. The track and hold circuit of claim 17, wherein the p-channel and n-channel transistors of each of the pair of dual pump circuits have equivalent sizes.

21. The track and hold circuit of claim 17, wherein the p-channel and n-channel transistors of each of the pair of dual pump circuits have equivalent conductances.

22. The track and hold circuit of claim 17, wherein the n-channel and p-channel pump circuits each comprise:

a MOS transistor having a control terminal and a pair of current terminals coupled between a supply voltage and a bias current source device;

an operational amplifier coupled in a source follower configuration having a first polarity input receiving a corresponding polarity of the differential input signal, a second polarity input coupled to the bias current source device and an output coupled to the control terminal of the MOS transistor;

a first switch having a common terminal and a switching terminal that switches at a predetermined rate between a common mode voltage and the output of the operational amplifier;

a second switch having a common terminal and a switching terminal that switches at the predetermined rate between the supply voltage and the control terminal of a corresponding device of the transmission gate;

a sampling capacitor coupled between the common terminals of the first and second switches;

the first and second switches switching such that the first switch selects the common mode voltage while the second switch selects supply voltage to charge the sampling capacitor with a difference voltage between the supply voltage and the common mode voltage, and then switches so that the first switch selects the output of the operational amplifier while the second switch selects the control terminal of the corresponding one of the transmission gate devices; and

a common mode MOS transistor coupled to apply the common mode voltage to the control terminal of the corresponding one of the transmission gate devices while the second switch selects the supply voltage.