Programmable input range SAR ADC
First Claim
1. A programmable input voltage range analog-to-digital converter comprising:
- a successive approximation analog-to-digital converter (SAR ADC) having a characteristic dynamic range;
an input voltage scaling network in which the input voltage is sampled onto one or more selected sampling capacitors to scale the input voltage to substantially match the characteristic dynamic range of the SAR ADC; and
a network of high voltage sampling switches interposed between the input voltage and the input voltage scaling network.
1 Assignment
0 Petitions
Accused Products
Abstract
A programmable input voltage range analog-to-digital converter in which a split gate oxide process allows the use of high voltage (±15 volt) switches on the same silicon substrate as standard sub-micron 5 volt CMOS devices. With this process, the analog input voltage can be sampled directly onto one or more sampling capacitors without the need for prior attenuation circuits. By only sampling on a given ratio of the sampling capacitors, the analog input can be scaled or attenuated to suit the dynamic range of the SAR (successive approximation register) ADC itself. In the system of the present invention, the sampling capacitor can be the actual capacitive redistribution digital-to-analog converter (CapDAC) used in the SAR ADC itself, or a separate capacitor array. By selecting which bits of the CapDAC or separate sampling array to sample on, one can program the input range. Once the analog input signal has been attenuated to match the allowed dynamic range of the SAR converter, traditional SAR techniques can be used to convert the input signal to a digital word.
44 Citations
24 Claims
-
1. A programmable input voltage range analog-to-digital converter comprising:
-
a successive approximation analog-to-digital converter (SAR ADC) having a characteristic dynamic range;
an input voltage scaling network in which the input voltage is sampled onto one or more selected sampling capacitors to scale the input voltage to substantially match the characteristic dynamic range of the SAR ADC; and
a network of high voltage sampling switches interposed between the input voltage and the input voltage scaling network. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A SAR ADC comprising:
-
a capacitive redistribution digital-to-analog converter (CapDAC) having an output coupled to a comparator;
SAR logic that controls iterative sampling of a SAR ADC input signal and monitors the output of the comparator;
an input voltage scaling network in which the input voltage is sampled onto one or more selected sampling capacitors to scale the input voltage to substantially match the characteristic dynamic range of the SAR ADC; and
a network of high voltage sampling switches interposed between the input voltage and the capacitive redistribution DAC, such that the input voltage is selectively sampled onto one or more of the capacitors of the CapDAC array. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
-
-
19. A SAR ADC comprising:
-
a capacitive redistribution digital-to-analog converter (CapDAC) having an output coupled to a comparator;
SAR logic that controls iterative sampling of a SAR ADC input signal and monitors the output of the comparator;
an input voltage scaling network in which the input voltage is sampled onto one or more selected sampling capacitors to scale the input voltage to substantially match the characteristic dynamic range of the SAR ADC;
a network of high voltage sampling switches interposed between the input voltage and the input voltage scaling network, such that the input voltage is selectively sampled onto one or more of the sampling capacitors;
range decoder logic that controls the network of high voltage sampling switches to select said one or more of the sampling capacitors; and
a range register to which a range selection control word is written, the range decoder logic being responsive to the range selection control word. - View Dependent Claims (20, 21, 22, 23, 24)
-
Specification