Graphics display system with window descriptors

• US 6,731,295 B1
• Filed: 11/09/1999
• Issued: 05/04/2004
• Est. Priority Date: 11/09/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh Jeffrey, Kranawetter, Greg A., Patterson, James T., Xie, Xiaodong
• Primary Examiner(s): Luu, Matthew
• Assistant Examiner(s): CHUNG, DANIEL J
• Application Number:
  US09/437,716
• Time in Patent Office: 1,638 Days
• Field of Search: 345/581, 345/589, 345/602, 345/549, 345/593, 345/601, 345/600, 345/781, 345/783, 345/806
• US Class Current: 345/581
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 : characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 : using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 : Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/59 : involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/440263 : by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/04 : Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0122 : the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers

Abstract

A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip uses window descriptors to describe logical surfaces, or windows, of graphics information to be displayed on the screen. The chip incorporates a unified memory architecture that provides a high level of system performance while conserving memory bandwidth and chip size. Video and graphics scaling capabilities as well as anti-flutter filtering capability are provided.

Claims

1. A data structure for representing graphics images arranged in logical surfaces to be displayed, each data structure describing a corresponding logical surface, the data structure comprising:

a field indicating relative depth of the corresponding logical surface on a display;

a field indicating an alpha value for the graphics image on the corresponding logical surface;

a field indicating a location of the corresponding logical surface on the display;

a field indicating a location in memory where graphics data for the corresponding logical surface is stored; and

a field indicating a color of the corresponding logical surface,

wherein the data structure is copied from a first memory to a second memory and sorted with other data structures in the second memory according to the relative depth of the corresponding logical surface on the display and based on which data structure in the second memory has been processed on a current display line, and

wherein at least one of the graphics images includes pixels having a single color, and wherein the pixels having the single color are generated at a display time using content of the color indicating field rather than previously stored in a graphics memory.

2. The data structure for representing graphics images arranged in logical surfaces for display of claim 1, the data structure further comprising a field indicating a format of the graphics data to be displayed on the corresponding logical surface.

3. The data structure for representing graphics images arranged in logical surfaces for display of claim 2 wherein the format of the graphics data to be displayed on the corresponding logic surface is selected from YUV, RGB, CLUT and alpha-only formats.

4. The data structure for representing graphics images arranged in logical surfaces for display of claim 3 wherein the alpha-only format is a format in which the graphics data represent alpha values only.

5. The data structure for representing graphics images arranged in logical surfaces for display of claim 1, the data structure further comprising a field indicating a method of selecting an alpha value for each pixel in the graphics image on the corresponding logical surface.

6. The data structure for representing graphics images arranged in logical surfaces for display of claim 5 wherein the alpha value for each pixel is selected using chroma keying, CLUT alpha values, luminance (Y) values or a window alpha value.

7. The data structure for representing graphics images arranged in logical surfaces for display of claim 1, wherein the alpha value contained in the field indicating the alpha value is applied to all pixels of the graphics image on the corresponding logical surface.

8. The data structure for representing graphics images arranged in logical surfaces for display of claim 1, the data structure further comprising a field indicating the number of pixels to be blanked out at the beginning of the display line.

18. The method of using a data structure to represent graphics images arranged in logical surfaces for display of claim 1, wherein the first memory comprises a system memory and the second memory resides in a windows controller in which the sorting of the data structures takes place.

20. The method of using a data structure to represent graphics images arranged in logical surfaces for display of claim 1, wherein a content of the relative depth field of the corresponding logical surface in the second memory is changed after the corresponding logical surface has been procesed on the current display line to indicate that the corresponding logical surface is not to be processed again on the current display line.

21. The data structure for representing graphics images arranged in logical surfaces for display of claim 20, wherein said graphics image of the corresponding logical surface on the current display line is blended with at least one other said graphics image on the current display line or rendered on the current display line of a display during processing of the corresponding logical surface.

9. A method of using a data structure to represent graphics images arranged in logical surfaces to be displayed, at least one of the graphics images including pixels having a single color, each data structure describing a corresponding logical surface, the method comprising the steps of:

indicating, in the data structure, relative depth of a corresponding logical surface on a display;

indicating, in the data structure, an alpha value for the graphics image on the corresponding logical surface;

indicating, in the data structure, a location of the corresponding logical surface on the display;

indicating, in the data structure, a location in memory where graphics data for the corresponding logical surface is stored;

indicating in the data structure, a color of the corresponding logical surface;

copying the data structure from a first memory to a second memory;

sorting the data structure with other data structures in the second memory according to the relative depth of the corresponding logical surface on the display and based on which data structure in the second memory has been processed on a current display line; and

generating the pixels having the single color for the at least one of the graphics images at a display time using the color of the corresponding logical surface indicated in the data structure.

10. The method of using a data structure to represent graphics images arranged in logical surfaces for display of claim 9 further the step of indicating, in the data structure, a format of the graphics data to be diplayed on the corresponding logical surface.

11. The method of using a data structure to represent graphics images arranged in logical surfaces for display of claim 10 wherein the format of the graphics data to be displayed on the corresponding logical surface is selected from YUV, RGB, CLUT and alpha-only formats.

12. The method of using a data structure to represent graphics images arranged in logical surfaces for display of claim 11 wherein the alpha-only format is a format in which the graphics data represent alpha values only.

13. The method of using a data structure to represent graphics images arranged in logical surfaces for display of claim 9 further comprising the step of indicating, in the data structure, a method of selecting an alpha value for each pixel in the graphics image on the corresponding logical surface.

14. The method of using a data structure to represent graphics images arranged in logical surfaces for display of claim 13 wherein the alpha value for each pixel is selected using chroma keying, CLUT alpha values, luminance *Y) values or a window alpha value.

15. The method of using a data structure to represent graphics images arranged in logical surfaces for display of claim 9 further comprising the step of applying the alpha value for the graphics in the logical surface to all pixels of the graphics image on the corresponding logical surface.

16. The method of using a data structure to represent graphics images arranged in logical surfaces for display of claim 9, wherein the alpha values for the graphics image on the corresponding logical surface is applied to all pixels of the graphics image on the corresponding logical surface.

17. The method of using a data structure to represent graphics images arranged in logical surfaces for display of claim 9 further comprising the step of indicating, in the data structure, a field indicating the number of pixels to be blanked out at the beginning of the display line.

19. The data structure for representing graphics images arranged in logical surfaces for display of claim 9, wherein the first memory comprises a system memory and the second memory resides in a windows controller in which the sorting of the data structures takes place.

22. The method of using a data structure to represent graphics images arranged in logical surfaces for display of claim 9, further comprising changing the relative depth indication of the corresponding logical surface in the second memory after the corresponding logical surface has been processed on the current display line to indicate that the corresponding logical surface is not to be processed again on the current display line.

23. The method of using a data structure to represent graphics images arranged in logical surfaces for display of claim 22, wherein said processing the corresponding logical surface comprises blending said graphics image of the corresponding logical surface on the current display line with at least one other said graphics image on the current display line or rendering said graphics image of the corresponding logical surface on the current display line on a display.