Non-volatile semiconductor memory device having shared row selection circuit

• US 6,731,540 B2
• Filed: 08/15/2002
• Issued: 05/04/2004
• Est. Priority Date: 08/28/2001
• Status: Expired due to Term

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jin-Yub, Lee, June
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/222,573
• Publication Number:
  US 20030043686A1
• Time in Patent Office: 628 Days
• Field of Search: 365/185.17, 365/185.11, 365/185.12, 365/185.13, 365/185.18, 365/185.03, 365/185.06
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits

Abstract

A NAND flash memory device includes a first and second memory blocks. A shared row selection circuit is provided between the first and second memory blocks, selectively or simultaneously selecting the first and second memory blocks, and transferring wordline voltages to a selected memory block by means in a multi-boosting manner.

Claims

1. A NAND flash memory device comprising:

first and second memory blocks each including a plurality of strings, each of the strings including a first selection transistor coupled to a first selection line, a second selection transistor coupled to a second selection line, and memory cells serially connected between the first and second selection transistors, the memory cells each being coupled to corresponding wordlines, respectively;

a logic circuit for generating a block selection signal in response to block selection information;

a precharge circuit for receiving first high, second high, and third high voltages and for charging a block wordline to the third high voltage without voltage drop when the block selection signal is activated;

a control transistor turned off when the block selection signal is activated, the control transistor being commonly connected to first selection lines of the first and second memory blocks;

a first switch circuit for transferring a first group of selection signals to wordlines of the first memory block, the first switch circuit being coupled to the block wordline and the first switch circuit including a plurality of first pass transistors having gates commonly connected to the block wordline; and

a second switch circuit for transferring a second group of selection signals to wordlines of the second memory block, the second switch circuit being coupled to the block wordline, and the second switch circuit including a plurality of second pass transistors having gates commonly connected to the block wordline.

2. The NAND flash memory device as recited in claim 1, further comprising a discharge transistor for discharging a voltage of the block wordline when the block selection signal is inactivated.

3. The NAND flash memory device as recited in claim 1, wherein the precharge circuit comprises:

an internal node;

a first switch for precharging the internal node according to the second high voltage, the first switch being connected between the first high voltage and the internal node; and

a second switch for transferring the third high voltage to the block wordline according to a voltage of the internal node, the second switch being connected between the third high voltage and the block wordline, wherein the block wordline is structured to be precharged in a multi-boosting manner.

4. The NAND flash memory device as recited in claim 3, wherein the multi-boosting manner comprises:

precharging the internal node using the first high voltage;

floating the precharge internal node; and

applying the third high voltage to the second switch to cause a boost of a voltage of the internal node.

5. The NAND flash memory device as recited in claim 1, wherein, when the first memory block is selected, the first switch circuit is structured to transfer the first group of the selection signals to the wordlines of the first memory block.

6. The NAND flash memory device as recited in claim 1, wherein when the second memory block is selected, the second switch circuit is structured to transfer the second group of the selection signals to the wordlines of the second memory block.

7. The NAND flash memory device as recited in claim 1, wherein when the first and second memory blocks are selected at the same time, the first switch circuit is structured to transfer the first group of the selection signals to the wordlines of the first memory block and the second switch circuit is structured to transfer the second group of the selection signals to the wordlines of the second memory block.

8. A NAND flash memory device comprising:

first and second memory blocks each including a plurality of strings, each of the strings including a first selection transistor coupled to a first selection line, a second selection transistor coupled to a second selection line, and memory cells serially connected between the first and second selection transistors, the memory cells each being coupled to corresponding wordlines, respectively;

a logic circuit for generating a block selection signal in response to block selection information;

a precharge circuit for receiving a first high, a second high, and a third high voltage and for charging first and second block wordlines, electrically isolated from each other, to the third high voltage without voltage drop when the block selection signal is activated;

a control transistor structured to be turned off when the block selection signal is activated, the control transistor being commonly connected to first selection lines of the first and second memory blocks;

a first switch circuit for transferring a first group of selection signals to wordlines of the first memory block, the first switch circuit being coupled to the block wordline and the first switch circuit including a plurality of first pass transistors having gates commonly connected to the block wordline; and

a second switch circuit for transferring a second group of selection signals to wordlines of the second memory block, the second switch circuit being coupled to the block wordline, and the second switch circuit including a plurality of second pass transistors having gates commonly connected to the block wordline.

9. The NAND flash memory device as recited in claim 8, further comprising:

a first discharge transistor for discharging a voltage of the first block wordline when the block selection signal is inactivated; and

a second discharge transistor for discharging a voltage of the second block wordline when the block selection signal is inactivated.

10. The NAND flash memory device as recited in claim 8, wherein the precharge circuit includes first and second precharge blocks, each precharge block including:

an internal node;

a first switch for precharging the internal node according to the second high voltage, the first switch being connected between the first high voltage and the internal node; and

a second switch for transferring the third voltage to the block wordline according to a voltage of the internal node, the second switch being connected between the third high voltage and the block wordline, wherein the block wordline is structured to be precharged in a multi-boosting manner.

11. The NAND flash memory device as recited in claim 10, wherein the multi-boosting manner comprises:

precharging the internal node using the first high voltage;

floating the precharge internal node; and

applying the third high voltage to the second switch to cause a boost of a voltage of the internal node.

12. The NAND flash memory device as recited in claim 8, wherein, when the first memory block is selected, the first switch circuit is structured to transfer the first group of the selection signals to the wordlines of the first memory block.

13. The NAND flash memory device as recited in claim 8, wherein when the second memory block is selected, the second switch circuit is structured to transfer the second group of the selection signals to the wordlines of the second memory block.

14. The NAND flash memory device as recited in claim 8, wherein when the first and second memory blocks are selected at the same time, the first switch circuit is structured to transfer the first group of the selection signals to the wordlines of the first memory block and the second switch circuit is structured to transfer the second group of the selection signals to the wordlines of the second memory block.

15. A NAND flash memory device including first and second mats each having a plurality of memory blocks, wherein each of the memory blocks includes a first selection transistor coupled to a first selection line, a second selection transistor coupled to a second selection line, and memory cells serially connected between the first and second selection lines, the memory cells being respectively coupled to corresponding wordlines, the NAND flash memory device comprising:

a row selection circuit including a plurality of row selectors each corresponding to respective memory blocks of the first and second mats;

a mat selection circuit for generating first and second mat selection signals each corresponding to the first and second mats in response to mat selection information;

a predecoder circuit for generating wordline selection signals in response to wordline selection information; and

a transfer circuit for receiving the wordline selection signals and outputting first and second selection signals in response to the first and second mat selection signals,

wherein each of the row selectors is shared by corresponding memory blocks of the first and second mats, and each of the row selectors includes;

a logic circuit for generating a block selection signal in response to block selection information,

a precharge circuit for receiving first, second and third high voltages and for charging a block wordline to the third high voltage without voltage drop when the block selection signal is activated,

a control transistor structured to be turned off when the block selection signal is activated, the control transistor being commonly coupled to first selection lines of the first and second memory blocks,

a first switch circuit for transferring a first group of selection signals to wordlines of the first memory block, the first switch circuit being coupled to the block wordline, and the first switch circuit including a plurality of first pass transistors having gates commonly connected to the block wordline, and

a second switch circuit for transferring a second group of selection signals to wordlines of the second memory block, the second switch circuit being coupled to the block wordline, and the second switch circuit including a plurality of second pass transistors having gates commonly connected to the block wordline.

16. The NAND flash memory device as recited in claim 15, further comprising a discharge transistor structured to discharge a voltage of the block wordline when the block selection signal is inactivated.

17. The NAND flash memory device as recited in claim 15, wherein the precharge circuit includes:

an internal node;

a first switch for precharging the internal node according to the second high voltage, the first switch being connected between the first high voltage and the internal node; and

a second switch for transferring the third high voltage to the block wordline according to a voltage of the internal node, the second switch being connected between the third high voltage and the block wordline, wherein the block wordline is structured to be precharged in a multi-boosting manner.

18. The NAND flash memory device as recited in claim 17, wherein the multi-boosting manner comprises:

precharging the internal node using the first high voltage;

floating the precharged internal node; and

applying the third high voltage to the second switch to cause a voltage boost of the floated internal node.

19. The NAND flash memory device as recited in claim 15, wherein when the first mat is selected, the first switch circuit is structured to transfer the first group of the selection signals to wordlines of a selected memory block of the first mat.

20. The NAND flash memory device as recited in claim 15, wherein when the second mat is selected, the second switch circuit is structured to transfer the second group of the selection signals to wordlines of a selected memory block of the second mat.

21. The NAND flash memory device as recited in claim 15, wherein when the first and second mats are selected at the same time, the first switch circuit is structured to transfer the first group of the selection signals to wordlines of a selected memory block of the first mat and the second switch circuit is structured to transfer the second group of the selection signals to wordlines of a selected memory block of the second mat.

22. A NAND flash memory device including first and second mats each having a plurality of memory blocks, wherein each of the memory blocks includes a first selection transistor coupled to a first selection line, a second selection transistor coupled to a second selection line, and memory cells serially connected between the first and second selection lines, the memory cells respectively coupled to corresponding wordlines, the NAND flash memory device comprising:

a row selection circuit including a plurality of row selectors each corresponding to respective memory blocks of the first and second mats;

a mat selection circuit for generating first and second mat selection signals each corresponding to the first and second mats in response to mat selection information;

a predecoder circuit for generating wordline selection signals in response to wordline selection information; and

a transfer circuit for receiving the wordline selection signals and outputting first and second selection signals in response to the first and second mat selection signals,

wherein each of the row selectors is shared by corresponding memory blocks of the first and second mats, and each of the row selectors includes;

a logic circuit for generating a block selection signal in response to block selection information,

a precharge circuit for receiving first high, second high, and third high voltages, and for charging first and second block wordlines, electrically isolated from each other, to the third high voltage without voltage drop when the block selection signal is activated,

a control transistor structured to be turned off when the block selection signal is activated, the control transistor being commonly connected to first selection lines of the first and second memory blocks,

a first switch circuit for transferring a first group of selection signals to wordlines of the first memory block, the first switch circuit being coupled to the block wordline, and the first switch circuit including a plurality of first pass transistors having gates commonly connected to the block wordline, and

a second switch circuit for transferring a second group of selection signals to wordlines of the second memory block, the second switch circuit being coupled to the block wordline, and the second switch circuit including a plurality of second pass transistors having gates commonly connected to the block wordline.

23. The NAND flash memory device as recited in claim 22, further comprising:

a first discharge transistor for discharging a voltage of the first block wordline when the block selection signal is inactivated; and

a second discharge transistor for discharging a voltage of the second block wordline when the block selection signal is inactivated.

24. The NAND flash memory device as recited in claim 22, wherein the precharge circuit is structured to precharge the block wordlines in a multi-boosting manner.

25. The NAND flash memory device as recited in claim 22, wherein when the first mat is selected, the first switch circuit is structured to transfer the first group of the selection signals to wordlines of a selected memory block of the first mat.

26. The NAND flash memory device as recited in claim 22, wherein when the second mat is selected, the second switch circuit is structured to transfer the second group of the selection signals to wordlines of a selected memory block of the second mat.

27. The NAND flash memory device as recited in claim 22, wherein when the first and second mats are selected at the same time, the first switch circuit is structured to transfer the first group of the selection signals to wordlines of a selected memory block of the first mat and the second switch circuit is structured to transfer the second group of the selection signals to wordlines of a selected memory block of the second mat, and the selected memory blocks share a corresponding selector.

28. A NAND flash memory device including first and second mats each having a plurality of memory blocks, wherein each of the memory blocks includes a first transistor coupled to a first selection line, a second selection transistor coupled to a second selection line, and a plurality of strings serially connected between the first and second selection transistors, the strings being respectively coupled to wordlines, the NAND flash memory device comprising:

a row selection circuit including a plurality of row selectors each corresponding to respective memory blocks of the first and second mats;

a mat selection circuit for generating first and second mat selection signals each corresponding to the first and second mats in response to mat selection information;

a predecoder circuit for generating wordline selection signals in response to wordline selection information; and

a transfer circuit for receiving the wordline selection signals and outputting first and second selection signals in response to the first and second mat selection signals,

wherein each of the row selectors is shared by corresponding memory blocks of the first and second mats, and each of the row selectors includes;

a logic circuit for generating a block selection signal in response to block selection information,

a precharge circuit for receiving first, second and third high voltages, and for charging one of first and second block wordlines, electrically isolated from each other, to the third high voltage without voltage drop when the block selection signal is activated;

a control transistor structured to be turned off when the block selection signal is activated, the control transistor being commonly connected to first selection lines of the first and second memory blocks,

a first switch circuit for transferring a first group of selection signals to wordlines of the first memory block when the first block wordline is activated, the first switch circuit being coupled to the block wordline, and the first switch circuit including a plurality of first pass transistors having gates commonly connected to the block wordline, and

a second switch circuit for transferring a second group of selection signals to wordlines of the second memory block when the second block wordline is activated, the second switch circuit being coupled to the block wordline, and the second switch circuit including a plurality of second pass transistors having gates commonly connected to the block wordline.

29. The NAND flash memory device as recited in claim 28, further comprising:

a first discharge transistor for discharging a voltage of the first block wordline when the block selection signal is inactivated; and

a second discharge transistor for discharging a voltage of the second block wordline when the block selection signal is inactivated.

30. The NAND flash memory device as recited in claim 28, wherein the precharge circuit is structured to precharge one of the first and second block wordlines by using multi-boosting.