Circuit for accurate memory read operations

• US 6,731,542 B1
• Filed: 12/05/2002
• Issued: 05/04/2004
• Est. Priority Date: 12/05/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Achter, Michael, Le, Binh Q., Pauling, Chen, Cleveland, Lee
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/313,444
• Time in Patent Office: 516 Days
• Field of Search: 365/185.03, 365/185.21, 365/185.25
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A memory circuit arrangement for sensing current in a target cell during a read operation is disclosed. According to one exemplary embodiment, the memory circuit arrangement comprises the target cell and a first neighboring cell adjacent to the target cell. The first target cell has a first bit line connected to ground; the target cell also has a second bit line connected to a sensing circuit. The first neighboring cell shares the second bit line with the target cell; the first neighboring cell also has a third bit line connected to the sensing circuit during the read operation. The memory circuit arrangement results in increased error margins in a fast and accurate manner during the read operation of the target cell.

Claims

1. A memory circuit arrangement for sensing current in a target cell during a read operation, said memory circuit arrangement comprising:

said target cell having a first bit line connected to ground, said target cell having a second bit line connected to a sensing circuit;

a first neighboring cell adjacent to said target cell, said first neighboring cell sharing said second bit line with said target cell, said first neighboring cell having a third bit line connected to said sensing circuit during said read operation.

2. The memory circuit arrangement of claim 1 further comprising a second neighboring cell adjacent to said first neighboring cell, said second neighboring cell sharing said third bit line with said first neighboring cell, said second neighboring cell having a fourth bit line connected to a precharge circuit during said read operation.

3. The memory circuit arrangement of claim 2 further comprising a third neighboring cell adjacent to said second neighboring cell, said third neighboring cell sharing said fourth bit line with said second neighboring cell, said third neighboring cell having a fifth bit line connected to said precharge circuit during said read operation.

4. The memory circuit arrangement of claim 1 wherein each of said target cell and said first neighboring cell comprises a respective gate terminal connected to a common word line.

5. The memory circuit arrangement of claim 2 wherein each of said target cell, said first neighboring cell, and said second neighboring cell comprises a respective gate terminal connected to a common word line.

6. The memory circuit arrangement of claim 3 wherein each of said target cell, said first neighboring cell, said second neighboring cell, and said third neighboring cell comprises a respective gate terminal connected to a common word line.

7. The memory circuit arrangement of claim 1 wherein said target cell stores a first bit and a second bit.

8. A memory circuit arrangement comprising:

target cell means for storing at least one bit, said target cell means having a first bit line connected to ground, said target cell means having a second bit line connected to a sensing circuit;

first neighboring cell means for storing at least one bit, said first neighboring cell means sharing said second bit line with said target cell means, said first neighboring cell means having a third bit line connected to said sensing circuit during a read operation.

9. The memory circuit arrangement of claim 8 further comprising second neighboring cell means for storing at least one bit, said second neighboring cell means adjacent to said first neighboring cell means, said second neighboring cell means sharing said third bit line with said first neighboring cell means, said second neighboring cell means having a fourth bit line connected to a precharge circuit during said read operation.

10. The memory circuit arrangement of claim 9 further comprising third neighboring cell means for storing at least one bit, said third neighboring cell means adjacent to said second neighboring cell means, said third neighboring cell means sharing said fourth bit line with said second neighboring cell means, said third neighboring cell means having a fifth bit line connected to said precharge circuit during said read operation.

11. The memory circuit arrangement of claim 8 wherein each of said target cell means and said first neighboring cell means comprises a respective gate terminal connected to a common word line.

12. The memory circuit arrangement of claim 9 wherein each of said target cell means, said first neighboring cell means, and said second neighboring cell means comprises a respective gate terminal connected to a common word line.

13. The memory circuit arrangement of claim 10 wherein each of said target cell means, said first neighboring cell means, said second neighboring cell means, and said third neighboring cell means comprises a respective gate terminal connected to a common word line.

14. The memory circuit arrangement of claim 8 wherein said target cell means stores a first bit and a second bit.

15. A memory circuit arrangement for sensing current in a target cell during a read operation, said memory circuit arrangement comprising said target cell having a first bit line connected to ground, said target cell having a second bit line connected to a sensing circuit, said memory circuit arrangement being characterized by:

a first neighboring cell adjacent to said target cell, said first neighboring cell sharing said second bit line with said target cell, said first neighboring cell having a third bit line connected to said sensing circuit during said read operation.

16. The memory circuit arrangement of claim 15 further comprising a second neighboring cell adjacent to said first neighboring cell, said second neighboring cell sharing said third bit line with said first neighboring cell, said second neighboring cell having a fourth bit line connected to a precharge circuit during said read operation.

17. The memory circuit arrangement of claim 16 further comprising a third neighboring cell adjacent to said second neighboring cell, said third neighboring cell sharing said fourth bit line with said second neighboring cell, said third neighboring cell having a fifth bit line connected to said precharge circuit during said read operation.

18. The memory circuit arrangement of claim 15 wherein each of said target cell and said first neighboring cell comprises a respective gate terminal connected to a common word line.

19. The memory circuit arrangement of claim 16 wherein each of said target cell, said first neighboring cell, and said second neighboring cell comprises a respective gate terminal connected to a common word line.

20. The memory circuit arrangement of claim 17 wherein each of said target cell, said first neighboring cell, said second neighboring cell, and said third neighboring cell comprises a respective gate terminal connected to a common word line.