SRAM power-up system and method

• US 6,731,546 B2
• Filed: 01/21/2003
• Issued: 05/04/2004
• Est. Priority Date: 12/21/2001
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Ken W.
• Primary Examiner(s): Mai, Son L.
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US10/348,787
• Publication Number:
  US 20030133343A1
• Time in Patent Office: 469 Days
• Field of Search: 365/154, 365/156, 365/168, 365/188, 365/189.09, 365/189.11, 365/190, 365/202
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A power-up circuit for an SRAM, particularly a loadless 4-T SRAM cell having PMOS access transistors. The power-up circuit disables a current path to the digit lines in an array of SRAM cells during power-up of the SRAM. As a result, the SRAM cells cannot draw power from the digit lines during power-up if voltages on word lines in the array during power-up cause access transistors for the SRAM cells to become conductive.

Claims

1. In an array of SRAM cells arranged in rows and columns and having a pair of complementary digit lines for each column of the array coupled to respective access transistors for each SRAM cell, a method of controlling the power-up current drawn by the array, comprising:

applying a predetermined bias current to the digit lines in a normal mode; and

coupling the digit lines to a voltage that maintains the access transistors non-conductive in a power-up mode.

2. The method of claim 1 wherein a respective bias transistor is coupled between a supply node and each of the digit lines, and wherein the act of biasing the digit lines to a predetermined bias voltage in a normal mode comprises coupling a voltage to the gate of the bias transistor that renders the bias transistor conductive during the normal mode.

3. The method of claim 1 wherein a respective bias transistor is coupled between a supply node and each of the digit lines, and wherein the act of coupling the digit lines to a voltage that maintains the access transistors non-conductive in a power-up mode comprises coupling a voltage to the gate of the bias transistor that renders the bias transistor non-conductive in the power-up mode.

4. The method of claim 1 wherein a respective bias transistor is coupled between a supply voltage and each of the digit lines, wherein the act of biasing the digit lines to a predetermined bias voltage in a normal mode comprises coupling a voltage to the gate of the bias transistor that renders the bias transistor conductive during the normal mode, and wherein the act of coupling the digit lines to a voltage that maintains the access transistors non-conductive in a power-up mode comprises coupling a voltage to the gate of the bias transistor that renders the bias transistor non-conductive in the power-up mode.

5. The method of claim 4 wherein each of the SRAM cells comprise a loadless 4-T SRAM cell having PMOS access transistors, wherein each of the bias transistor comprises a PMOS transistor coupled to a positive supply voltage, wherein the act of coupling a voltage to the gate of the bias transistor that renders the bias transistor conductive during the normal mode comprises coupling substantially ground potential to the gate of the PMOS bias transistor in the normal mode, and wherein the act of coupling a voltage to the gate of the bias transistor that renders the bias transistor non-conductive in the power-up mode comprises coupling the gate of the PMOS bias transistor to substantially the positive supply voltage in the power-up mode.

6. The method of claim 1, wherein a respective bias transistor is coupled between a supply terminal and each of the digit lines, and wherein the act of biasing the digit lines to a predetermined bias voltage in a normal mode comprises coupling a supply voltage from the supply terminal each of the bias transistors.

7. The method of claim 6, wherein a respective bias transistor is coupled between a supply terminal and each of the digit lines, and wherein the act of coupling the digit lines to a voltage that maintains the access transistors non-conductive in a power-up mode comprises isolating the supply voltage from the supply terminal of each of the bias transistors.

8. The method of claim 1, wherein a respective bias transistor is coupled between a supply terminal and each of the digit lines, wherein the act of applying a predetermined bias current to the digit lines in a normal mode comprises coupling a supply voltage from the supply terminal each of the bias transistors, and wherein the act of coupling the digit lines to a voltage that maintains the access transistors non-conductive in a power-up mode comprises isolating the supply voltage from the supply terminal of each of the bias transistors.