Redundancy circuit and method for semiconductor memory devices

• US 6,731,550 B2
• Filed: 05/31/2002
• Issued: 05/04/2004
• Est. Priority Date: 05/31/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: McClure, David C.
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US10/161,501
• Publication Number:
  US 20030223282A1
• Time in Patent Office: 704 Days
• Field of Search: 365/200, 365/230.06, 365/230.02, 365/230.03, 365/185.09, 365/185.08
• US Class Current: 365/200
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A redundancy circuit and method are disclosed for replacing at least one defective memory cell in a memory device. The redundancy circuit may include redundant decode circuitry for selectively maintaining an address of a defective memory cell in the memory device, receiving the input address and generating an output signal having a value indicative of whether the input address corresponds to the address of the defective memory cell. The redundancy circuit may further include a plurality of redundant storage circuits for selectively maintaining data values, and redundant control circuitry for selectively and individually accessing a first of the redundant storage circuits based upon the value of the output signal of the redundant decode circuitry.

Claims

1. A memory device, comprising:

an array of memory cells, each memory cell being capable of maintaining a data value therein;

address decode circuitry for receiving an input address and selecting a plurality of memory cells based upon the value of the input address;

redundant decode circuitry for selectively maintaining an address of defective memory cells in the array, receiving the input address and generating an output signal having a value indicative of whether the input address corresponds to the address of a defective memory cell,

a plurality of redundant storage cells, each for selectively maintaining data values;

redundant control circuitry for selectively and individually accessing a first of the redundant storage cells based upon the value of the output signal of the redundant decode circuitry to replace the defective memory cell in the addressed plurality of memory cells.

2. The memory device of claim 1, wherein delays related to accessing the first redundant storage cell are substantially the same as delays related to accessing the array of memory cells.

3. The memory device of claim 1, wherein the memory device is a volatile memory device and the redundant storage cells are latch circuits.

4. The memory device of claim 3, wherein the array of memory cells is a static random access memory device.

5. The memory device of claim 1, wherein the array of memory cells is a non-volatile memory device and the redundant storage cells are circuits capable of storing a data value in a non-volatile manner.

6. The memory device of claim 1, wherein:

the memory device includes an external data port and the memory device further comprises a multiplexer circuit disposed between the first redundant storage cell and the external data port.

7. The memory device of claim 6, wherein the external data port of the memory device is capable of outputting data values stored in the addressed memory cells, except for the defective memory cell, along with the data value stored in the first redundant storage cell of the memory device.

8. The memory device of claim 1, wherein:

the memory device includes an external data port and the memory device further comprises a multiplexer circuit disposed between an input of the first redundant storage cell and the external data port.

9. The memory device of claim 1, further comprising:

a plurality of external data ports; and

first circuitry for selectively coupling the first redundant storage cell to any of the external data ports.

10. The memory device of claim 1, further comprising:

the redundant decode circuitry selectively maintaining an address of a second defective memory cell in the array, receiving the input address and generating an output signal having a value indicative of the input address corresponding to the address of the second defective memory cell; and

wherein a second of the redundant storage cells is coupled to the redundant control circuitry which selectively and individually accesses the second redundant storage cell based upon the value of the output signal of the second redundant decode circuitry to replace the second defective memory cell in the addressed plurality of memory cells.

11. The memory device of claim 10, wherein the memory device includes a plurality of external data ports, and each of the first and second redundant storage cells are coupled to a distinct external data port.

12. The memory device of claim 10, wherein the memory device includes an external data port, the memory device further includes a multiplexer circuit coupled between the first and second redundant storage cells and the external data port.

13. The memory device of claim 1, wherein the redundant storage cells are not located in the array of memory cells.

14. A method of performing a memory access operation in a memory device having an array of memory cells and at least one redundant storage cell, comprising:

receiving an input address signal;

comparing the input address signal with an address of defective memory cells in the memory device; and

upon an affirmative determination that the input address signal corresponds to the address of a defective memory cell, individually accessing the redundant storage cell, along with non-defective ones of the addressed memory cells, to replace the defective memory cell, the step of accessing occurring with substantially the same timing as to both the non-defective memory cells and the redundant storage cell.

15. The method of claim 14, wherein the step of accessing the redundant storage cell comprises coupling an output of the redundant storage cell to an external data port of the memory device.

16. The method of claim 14, wherein the step of accessing the redundant storage cell comprises coupling an input of the redundant storage cell to an external data port of the memory device.

17. The method of claim 14, wherein the step of accessing further comprises latching a data value provided to the memory device into the redundant storage cell.

18. A computing apparatus, comprising:

a processing element; and

a memory device coupled to the processing element for storing information, comprising;

a plurality of memory cells, the memory cells including a defective memory cell;

decode circuitry for receiving an address input provided to the memory device and selecting a plurality of memory cells, including both non-defective memory cells and the defective memory cell, based upon the address input received;

a redundant storage cell capable of maintaining a data value;

redundant detection circuitry for comparing the address input with an address of the defective memory cell;

an external data port; and

circuitry coupled to the redundant storage cell for selectively and individually accessing the redundant storage cell based upon the comparison to replace the defective memory cell along with accessing the addressed non-defective memory cells.

19. The computing apparatus of claim 18, wherein the plurality of memory cells are a volatile memory device and the redundant storage cell is a latch circuit.

20. The computing apparatus of claim 18, wherein the redundant storage cell includes at least one logic gate.

21. The computing apparatus of claim 18, wherein the circuitry comprises a multiplexer circuit coupled between the redundant storage cell and the external data port and between the memory cells and the external data port.

22. The computing apparatus of claim 18, further comprising:

second redundant detection circuitry for comparing the address input with a second address corresponding to a second defective memory cell in the plurality of memory cells; and

a second redundant storage cell capable of maintaining a data value, wherein the circuitry selectively and individually accesses the second redundant storage cell based upon the comparison by the second redundant detection circuitry to replace the second defective memory cell along with accessing the addressed non-defective memory cells.

23. The computing apparatus of claim 22, wherein the memory device includes first and second external data ports, and the redundant storage cell is coupled to the first external data port and the second redundant storage cell is coupled to the second external data port.

24. The computing apparatus of claim 22, wherein the data circuitry includes a multiplexer coupled between the redundant storage cell and the external data port and between the second redundant storage cell and the external data port.

25. The computing apparatus of claim 18, wherein the memory cells are arranged in an array, and the redundant storage cell is spaced from the array of memory cells.

26. A memory device, comprising:

a plurality of memory cells, the memory cells including a defective memory cell;

decode circuitry for receiving an address input provided to the memory device and selecting a plurality of memory cells including non-defective memory cells and the defective memory cell based upon the address input received;

a redundant storage cell capable of maintaining a data value;

redundant detection circuitry for comparing the address input with an address of the defective memory cell;

an external data port; and

circuitry coupled to the redundant storage cell for selectively and individually accessing the redundant storage cell based upon the comparison to replace the defective memory cell along with accessing of the addressed non-defective memory cells.

27. The memory device of claim 26, wherein the plurality of memory cells is a volatile memory device and the redundant storage cell is a latch circuit.

28. The memory device of claim 26, wherein the redundant storage cell includes at least one logic gate.

29. The memory device of claim 26, wherein the circuitry comprises a multiplexer circuit coupled between the redundant storage cell and the external data port and between the memory cells and the external data port.

30. The memory device of claim 26, further comprising:

second redundant detection circuitry for comparing the address input with a second address corresponding to a second defective memory cell in the plurality of memory cells; and

a second redundant storage cell capable of maintaining a data value, wherein the circuitry selectively and individually accesses the second redundant storage cell based upon the comparison by the second redundant detection circuitry to replace the second defective memory cell along with accessing of the addressed non-defective memory cells.

31. The memory device of claim 30, wherein the memory device includes first and second external data ports, and the redundant storage cell is coupled to the first external data port and the second redundant storage cell is coupled to the second external data port.

32. The memory device of claim 30, wherein the data circuitry includes a multiplexer coupled between the redundant storage cell and the external data port and between the second redundant storage cell and the external data port.

33. A memory device, comprising:

a plurality of memory cells, the memory cells including a defective memory cell;

decode circuitry for receiving an address input provided to the memory device and selecting a plurality of memory cells including non-defective memory cells and the defective memory cell;

a redundant storage cell, separate from the memory cells, capable of maintaining a data value;

redundant detection circuitry for comparing the address input with an address of the defective memory cell;

an external data port; and

means, coupled to the redundant storage cell, for selectively and individually replacing, during the course of a memory access operation, the defective memory cell with the redundant storage cell based upon the comparison while accessing the non-defective memory cells.

34. A memory device, comprising:

a memory array including a plurality of memory cells,

at least one redundant memory cell; and

a circuit that detects when an addressed one of the plurality of memory cells is defective and instead addresses, along with addressed non-defective memory cells in the memory array, the at least one redundant memory cell as a replacement for the defective memory cell.

35. A method for accessing a memory device including a memory array having a plurality of memory cells and at least one redundant memory cell, comprising:

detecting when an addressed one of the plurality of memory cells is defective; and

addressing, along with addressed non-defective memory cells in the memory array, the at least one redundant memory cell as a replacement for the defective memory cell.