Method of refreshing an electrically erasable and programmable non-volatile memory

• US 6,731,557 B2
• Filed: 06/20/2002
• Issued: 05/04/2004
• Est. Priority Date: 06/21/2001
• Status: Expired due to Fees

• Current Assignee: MacLean-Fogg Company, STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Beretta, Franco Enrico
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/176,387
• Publication Number:
  US 20030012064A1
• Time in Patent Office: 684 Days
• Field of Search: 365/222, 365/185.22
• US Class Current: 365/222
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

A method (1110a;1110b) of refreshing an electrically erasable and programmable non-volatile memory (100) having a plurality of memory cells (Mhk) is proposed. The method includes the steps of: verifying (1106-1114; 1152-1162) whether a memory cell has drifted from a correct condition (i.e., a predetermined voltage and/or voltage range), and individually restoring (1116-1130) the correct condition of the memory cell if the result of the verification is positive.

Claims

1. A method of refreshing an electrically erasable and programmable non-volatile memory comprising:

verifying, during a refresh process, whether a memory cell has drifted from a predetermined voltage; and

individually restoring a corrected voltage of the memory cell if the memory cell has drifted from the predetermined voltage.

2. The method according to claim 1, wherein the verifying whether a memory cell has drifted from a predetermined voltage includes each of the memory cell stores one of a plurality of different logic values defined by an electric characteristic of the memory cell, and whereby each pair of adjacent logic values of the plurality of different logic values being delineated by a corresponding reference value.

3. The method according to claim 2, wherein the wherein the verifying whether a memory cell has drifted from a predetermined voltage includes verifying each reference value is associated with a first guard valise and a second guard value defining a warning zone around the reference value;

and

wherein the verifying whether the memory cell has drifted from a predetermined voltage includes determining that the electric characteristic has drifted in one of;

a first direction located between a current reference value and the corresponding first guard value; and

a second direction located between the current reference value and the corresponding second guard value.

4. The method according to claim 3, wherein the verifying whether the memory cell has drifted from a predetermined voltage includes determining that the electric characteristic has drifted in one of the first direction and the second direction includes comparing the electric characteristic simultaneously with the current reference value, the corresponding first guard value and the corresponding second guard value.

5. The method according to claim 3, wherein the verifying whether the memory cell has drifted from a predetermined voltage includes determining that the electric characteristic has drifted in one of the first direction and the second direction further includes:

providing at least one value of a set consisting of the current reference value, the corresponding first guard value and the corresponding second guard value; and

obtaining each other value of the net from the at least one provided value.

6. The method according to claim 4, wherein the verifying whether the memory cell has drifted from a predetermined voltage includes determining that the electric characteristic has drifted in one of the first direction and the second direction further includes:

providing at least one value of a set consisting of the current reference value, the corresponding first guard value and the corresponding second guard value; and

obtaining each other value of the set from the at least one provided value.

7. The method according to claim 2, wherein the verifying whether the memory cell has drifted from a predetermined voltage includes:

reading a value stored in the memory cell;

correcting the value stored by means of a corresponding error correction code; and

determining that the electric characteristic has drifted in one of a first direction and a second direction according to a comparison with the reference value associated with the corrected voltage.

8. The method according to claim 4, wherein the verifying whether the memory cell has drifted from a predetermined voltage includes:

reading a value stored in the memory cell;

correcting the value stored by means of a corresponding error correction code; and

determining that the electric characteristic has drifted in one of the first direction and the second direction according to a comparison with the reference value associated with the corrected voltage.

9. The method according to claim 6, wherein the verifying whether the memory cell has drifted from a predetermined voltage includes:

reading a value stored in the memory cell;

correcting the value stored by means oh corresponding error correction code; and

determining that the electric characteristic has drifted in one of the first direction and the second direction according to a comparison with the reference value associated with the corrected voltage.

10. The method according to claim 9, wherein the verifying whether the memory cell has drifted from a predetermined voltage includes verifying whether the memory cell has drifted from the predetermined voltage is performed during a reading procedure for outputting the corrected voltage.

11. The method according to claim from 3, wherein the individually restoring the corrected voltage includes:

applying a series of erasing pulses to the memory cell until the electric characteristic reaches the first guard value if the electric characteristic has drifted in the first direction; and

applying a series of programming pulses to the memory cell until the electric characteristic reaches the second guard value if the electric characteristic has drifted in the second direction.

12. The method according to claim from 4, wherein the individually restoring the corrected voltage includes:

applying a series of erasing pulses to the memory cell until the electric characteristic reaches the first guard value if the electric characteristic has drifted in the first direction; and

applying a series of programming pulses to the memory cell until the electric characteristic reaches the second guard value if the electric characteristic has drifted in the second direction.

13. The method according to claim from 6, wherein the individually restoring the corrected voltage includes:

applying a series of erasing pulses to the memory cell until the electric characteristic reaches the first guard value if the electric characteristic has drifted in the first direction; and

applying a series of programming pulses to the memory cell until the electric characteristic reaches the second guard value if the electric characteristic has drifted in the second direction.

14. The method according to claim from 8, wherein the individually restoring the corrected voltage includes:

applying a series of erasing pulses to the memory cell until the electric characteristic reaches the first guard value if the electric characteristic has drifted in the first direction; and

applying a series of programming pulses to the memory cell until the electric characteristic reaches the second guard value if the electric characteristic has drifted in the second direction.

15. The method according to claim from 9, wherein the individually restoring the corrected voltage includes:

applying a series of erasing pulses to the memory cell until the electric characteristic reaches the first guard value if the electric characteristic has drifted in the first direction; and

applying a series of programming pulses to the memory cell until the electric characteristic reaches the second guard value if the electric characteristic has drifted in the second direction.

16. The method according to claim from 10, wherein the individually restoring the corrected voltage includes:

applying a series of erasing pulses to the memory cell until the electric characteristic reaches the first guard value if the electric characteristic has drifted in the first direction; and

applying a series of programming pulses to the memory cell until the electric characteristic reaches the second guard value if the electric characteristic has drifted in the second direction.

17. The method according to claim 16, wherein the plurality of logic values consist of more than two logic values, and the individually restoring the corrected voltage further includes:

after applying the series of erasing pulses, then applying a series of further programming pulses to the memory cell if the electric characteristic has reached a next second guard value in the second direction; and

after applying the series of programming pulses, then applying a series of further erasing pulses to the memory cell if the electric characteristic has reached a next first guard value in the first direction.

18. An electrically erasable and programmable non-volatile memory comprising:

a plurality of memory cells;

means for verifying, during a refresh process, whether a memory cell has drifted from a predetermined voltage; and

means for individually restoring a corrected voltage of the memory cell if the memory cell has drifted from the predetermined voltage.

19. The memory of claim 18, Wherein the means for verifying is a current sense amplifier.

20. The memory of claim 18, wherein the means far individually restoring is a refreshing unit.