Fibre channel switching system and method

• US 6,731,646 B1
• Filed: 10/13/2000
• Issued: 05/04/2004
• Est. Priority Date: 03/21/1997
• Status: Expired due to Fees

• Current Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Original Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Inventors: Banks, David C., Stoevhase, Bent, Farnworth, Steven L., Ramsay, Paul
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): Boakye, Alexander O.
• Application Number:
  US09/687,933
• Time in Patent Office: 1,299 Days
• Field of Search: 370/412, 370/422, 370/429, 370/380, 370/384, 370/392, 370/402, 370/396, 370/394
• US Class Current: 370/422
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/357 Fibre channel switches

Abstract

A modular Fibre Channel switch includes a data switching path and a message switching path to provide logical point to point connections between switch ports. The data switching path includes a bank of shared SRAM memory devices that are accessed in a time-sliced protocol by each switch port. A receiving switch port writes a data frame to the bank of shared SRAM and the transmitting switch port then reads the data frame from the shared SRAM thereby effecting the logical point to point connection. Because the switch port includes a frame logic circuit that allows for an arbitrary start of frame address, each frame can be written to the first available DRAM device thus eliminating the need to buffer the data frame while waiting for a predetermined DRAM device to cycle in the time sliced protocol. The message switching path includes a message crossbar switch that is barrel shifted in a time sliced fashion to effect message passing among the switch ports. The switch includes a motherboard containing an embedded G_Port ASIC, a message crossbar switch to handle message passing and shared memory that is used to perform data switching. The switch also includes a central processing unit daughter board and external switch port daughter boards.

Claims

1. A switch fabric comprising a plurality of interconnected switches, at least one of said plurality of switches temporarily storing a data frame received at a receive port of a plurality of fiber optic ports, the switch including:

a central memory including a plurality of memory modules;

a data path control circuit for sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module, wherein the data path control circuit couples the receive port to the memory modules frequently enough to support continuous writing of data from the receive port to the central memory, and

a port circuitry for writing a portion of the data frame from the receive port to ones of the memory modules during the timeslot allocated for such writing, wherein the data frame is written across the memory modules.

2. The fabric of claim 1 wherein the data path control circuit couples the receive port to the memory modules frequently enough to support continuous writing of data from the receive port to the central memory and couples the transmit port to the memory modules frequently enough to support continuous reading of data from the central memory to the transmit port.

3. A switch fabric comprising a plurality of interconnected switches, at least one of said plurality of switches temporarily storing a data frame received at a receive port of a plurality of fiber optic ports, the switch including:

a central memory including a plurality of memory modules;

a data path control circuit for sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module; and

a port circuitry for writing a first portion of the data frame to a first memory module during a first available timeslot; and

further for writing the remaining portions of the data frame to other memory modules during subsequent timeslots.

4. A switch fabric comprising a plurality of interconnected switches, at least one of said plurality of switches temporarily storing a data frame received at a receive port of a plurality of fiber optic ports and destined for a transmit port of the plurality of fiber optic ports, the switch including:

a central memory including a plurality of memory modules;

a data path control circuit for

sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module; and

sequentially coupling the transmit port to ones of the memory modules during a timeslot allocated for reading from the memory module to the transmit port; and

a port circuitry for

writing a portion of the data frame from the receive port to ones of the memory modules during the timeslot allocated for such writing, wherein the data frame is written across the memory modules, wherein for each memory module the timeslots allocated for writing to the memory module are contiguous in time; and

reading a portion of the data frame from the individual memory modules to the transmit port during the timeslot allocate for such reading, wherein the data frame is read to the transmit port, wherein for each memory module the timeslots allocated for reading from the memory module are contiguous in time.

5. The fabric of claim 4 wherein the contiguous timeslots allocated for writing are separated from the timeslots allocated for reading by at least one timeslot.

6. A switch fabric comprising a plurality of interconnected switches, at least one of said plurality of switches retrieving a temporarily stored data frame destined for a transmit port of a plurality of fiber optic ports, the switch including:

a central memory including a plurality of memory modules for storing a data frame across the memory modules;

a data path control circuit for sequentially coupling the transmit port to ones of the memory modules during a timeslot allocated for reading from the memory module to the transmit port, wherein the data path control circuit couples the transmit port to the memory modules frequently enough to support continuous reading of data from the central memory to the transmit port; and

a port circuitry for reading a portion of the data frame from the memory module to the transmit port during the timeslot allocated for such reading, wherein the data frame is read to the transmit port.

7. A switch fabric comprising a plurality of interconnected switches, at least one of said plurality of switches switching a data frame from a receive port of a plurality of fiber optic ports to a transmit port of the plurality of fiber optic ports, the switch including:

a central memory including a plurality of memory modules, and wherein the central memory is subdivided into a plurality of frame buffers, each frame buffer including a portion of each memory module;

a data path control circuit for sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module and further for sequentially coupling the transmit port to ones of the memory modules during a timeslot allocated for reading from the memory module to the transmit port, wherein the data path control circuit couples each port to each memory module in a regular sequence for writing to the memory module and couples each port to each memory module in a regular sequence for reading from the memory module, all of the timeslots being of equal duration;

a receive port circuitry for writing a portion of the data frame from the receive port to ones of the memory modules during the timeslot allocated for such writing, wherein the data frame is written to one of the frame buffers;

a message path for sending a message from the receive port to the transmit port indicating availability of the data frame in the central memory; and

a transmit port circuitry for, responsive to receipt of the message indicating availability of the data frame, reading the portions of the data frame from the ones of the memory modules to the transmit port during the timeslot allocated for such reading, wherein the data frame is read to the transmit port.

8. The fabric of claim 7 wherein:

a first portion of the data frame is written to a first memory module during a first available timeslot;

the remaining portions of the data frame are written to other memory modules during subsequent timeslots; and

the message identifies the first memory module and the frame buffer to which the data frame is written.