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Zero-delay buffer circuit for a spread spectrum clock system and method therefor

  • US 6,731,667 B1
  • Filed: 11/18/1999
  • Issued: 05/04/2004
  • Est. Priority Date: 11/18/1999
  • Status: Expired due to Term
First Claim
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1. A spread-spectrum clocking (SSC) system for generating an output clock signal having a reduced electromagnetic emission (EMI), comprising:

  • a SSC generator circuit that receives an input clock signal and generates a modulated frequency clock signal; and

    a zero-delay buffer circuit that receives and buffers said modulated frequency clock signal to generate an output clock signal, the zero-delay buffer circuit aligning a phase of the modulated frequency clock signal and the output clock signal such that there is no phase difference between the output clock signal and the modulated frequency clock signal, wherein the zero-delay buffer circuit is a delay-locked loop (DLL) circuit comprises;

    a phase detector device that receives the modulated frequency clock signal and the output clock signal to generate phase detector output signals indicative of a phase difference between the modulated frequency clock signal and the output clock signal;

    a charge pump circuit coupled to the phase detector device for receiving the phase detector output signals and generating charge pump signals;

    a loop filter circuit receiving the charge pump signals; and

    a voltage controlled delay chain (VCDC) circuit coupled to the loop filter and the phase detector, wherein the VCDC circuit aligns phases of the modulated frequency clock signal and the output clock signal, wherein the phase detector device further comprises;

    a first phase detector circuit that receives the modulated frequency clock signal and generates first and second pulse signals indicative of one of a rising edge and a falling edge of the modulated frequency clock signal and the output clock signal, respectively;

    a second phase detector circuit that receives the modulated frequency clock signal and generates third and fourth pulse signals indicative of one of the rising edge and the falling edge of the modulated frequency clock signal and the output clock signal, respectively; and

    a signal divider circuit to alternatively operate the first and second phase detector circuit in one of an operational mode and a reset mode, wherein the first phase detector comprises;

    first and second logic gates, an output of the first logic gate being coupled to a first input of the second logic gate and a second input of the second logic gate being coupled to a first output of the signal divider circuit, a first flip-flop coupled to a first input of the first logic gate, a constant signal, and an output of the second logic gate and responsive to the modulated frequency clock signal, a second flip flop coupled to a second input of the first logic gate, the constant signal, and the output of the second logic gate and responsive to the output clock signal;

    wherein the second phase detector circuit comprises;

    third and fourth logic gates, an output of the third logic gate being coupled to a first input of the fourth logic gate and a second input of the fourth logic gate being coupled to a second output of the signal divider circuit, a third flip flop coupled to a first input of a third logic gate, the constant signal, and an output of the fourth logic gate and responsive to the modulated frequency clock signal. a fourth flip flop coupled to a second input of the third logic gate, the constant signal, and the output of the fourth logic gate, and responsive to the output clock signal, and the signal divider circuit comprises a fifth flip-flop coupled to the modulated frequency clock signal and inputs of the second and fourth logic gates.

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