Zero-delay buffer circuit for a spread spectrum clock system and method therefor

• US 6,731,667 B1
• Filed: 11/18/1999
• Issued: 05/04/2004
• Est. Priority Date: 11/18/1999
• Status: Expired due to Term

• Current Assignee: AnaPass, Inc.
• Original Assignee: AnaPass, Inc.
• Inventors: Lee, Kyeongho, Park, Joonbae
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): ODOM, CURTIS B
• Application Number:
  US09/442,751
• Time in Patent Office: 1,629 Days
• Field of Search: 375/130, 375/375, 375/376, 375/373, 327/158, 331/25
• US Class Current: 375/130
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics
• CPC Class Codes: H04B 2215/067 by modulation dispersion

Abstract

A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers the modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

Claims

1. A spread-spectrum clocking (SSC) system for generating an output clock signal having a reduced electromagnetic emission (EMI), comprising:

a SSC generator circuit that receives an input clock signal and generates a modulated frequency clock signal; and

a zero-delay buffer circuit that receives and buffers said modulated frequency clock signal to generate an output clock signal, the zero-delay buffer circuit aligning a phase of the modulated frequency clock signal and the output clock signal such that there is no phase difference between the output clock signal and the modulated frequency clock signal,

wherein the zero-delay buffer circuit is a delay-locked loop (DLL) circuit comprises;

a phase detector device that receives the modulated frequency clock signal and the output clock signal to generate phase detector output signals indicative of a phase difference between the modulated frequency clock signal and the output clock signal;

a charge pump circuit coupled to the phase detector device for receiving the phase detector output signals and generating charge pump signals;

a loop filter circuit receiving the charge pump signals; and

a voltage controlled delay chain (VCDC) circuit coupled to the loop filter and the phase detector, wherein the VCDC circuit aligns phases of the modulated frequency clock signal and the output clock signal,

wherein the phase detector device further comprises;

a first phase detector circuit that receives the modulated frequency clock signal and generates first and second pulse signals indicative of one of a rising edge and a falling edge of the modulated frequency clock signal and the output clock signal, respectively;

a second phase detector circuit that receives the modulated frequency clock signal and generates third and fourth pulse signals indicative of one of the rising edge and the falling edge of the modulated frequency clock signal and the output clock signal, respectively; and

a signal divider circuit to alternatively operate the first and second phase detector circuit in one of an operational mode and a reset mode,

wherein the first phase detector comprises;

first and second logic gates, an output of the first logic gate being coupled to a first input of the second logic gate and a second input of the second logic gate being coupled to a first output of the signal divider circuit,

a first flip-flop coupled to a first input of the first logic gate, a constant signal, and an output of the second logic gate and responsive to the modulated frequency clock signal,

a second flip flop coupled to a second input of the first logic gate, the constant signal, and the output of the second logic gate and responsive to the output clock signal;

wherein the second phase detector circuit comprises;

third and fourth logic gates, an output of the third logic gate being coupled to a first input of the fourth logic gate and a second input of the fourth logic gate being coupled to a second output of the signal divider circuit,

a third flip flop coupled to a first input of a third logic gate, the constant signal, and an output of the fourth logic gate and responsive to the modulated frequency clock signal.

a fourth flip flop coupled to a second input of the third logic gate, the constant signal, and the output of the fourth logic gate, and responsive to the output clock signal, and the signal divider circuit comprises a fifth flip-flop coupled to the modulated frequency clock signal and inputs of the second and fourth logic gates.

2. The zero-delay buffer circuit of claim 1 wherein the first and third logic gates are AND logic gates, and the second and fourth logic gates are OR logic gates.

3. A spread-spectrum clocking (SSC) system for generating an output clock signal having a reduced electromagnetic emission (EMI), comprising:

a SSC generator circuit that receives an input clock signal and generates a modulated frequency clock signal; and

a zero-delay buffer circuit that receives and buffers said modulated frequency clock signal to generate an output clock signal, the zero-delay buffer circuit aligning a phase of the modulated frequency clock signal and the output clock signal such that there is no phase difference between the output clock signal and the modulated frequency clock signal,

wherein the zero-delay buffer circuit is a delay-locked loop (DLL) circuit comprises;

a phase detector device that receives the modulated frequency clock signal and the output clock signal to generate phase detector output signals indicative of a phase difference between the modulated frequency clock signal and the output clock signal;

a charge pump circuit coupled to the phase detector device for receiving the phase detector output signals and generating charge pump signals;

a loop filter circuit receiving the charge pump signals; and

a voltage controlled delay chain (VCDC) circuit coupled to the loop filter and the phase detector, wherein the VCDC circuit aligns phases of the modulated frequency clock signal and the output clock signal,

wherein the VCDC circuit further comprises;

a delayed pulse generator that receives and delays the modulated frequency clock signal to generate a delayed modulated frequency clock signal, and generates a first output signal and a second output signal based on the delayed modulated frequency clock signal;

a first delay line circuit that receives the first output signal, a control signal and a second delay line circuit output signal indicative of a delay between the output clock signal and the modulated frequency clock signal, and generates a plurality of third output signals controlled by the control signal, wherein the third output signals are indicative of the delay between the output clock signal and the delayed modulated frequency clock signal;

a controller circuit that receives the second output signal and the third output signals and generates the control signal, wherein the control signal is indicative of a delay between the second output signal and the third output signals; and

a second delay line circuit that receives the control signal, the modified frequency clock signal and the phase detector output signal to generate the output clock signal and the second delay line circuit output signal.

4. The zero delay buffer circuit of claim 3, wherein the first delay line circuit further comprises:

a first coarse delay line circuit that receives the first output signal and the control signal and generates a first coarse delay line circuit output signal;

a first fine delay line circuit that receives the first coarse delay line circuit output signal and the second delay line circuit output signal and generates a first fine delay line circuit output signal; and

a first buffer circuit that receives the first fine delay line circuit output signal and generates the third output signals;

wherein the second delay line circuit comprises;

a second coarse delay line circuit that receives the modulated frequency output signal and the control signal and generates a second coarse delay line circuit output signal indicative of a delay between the modulated frequency clock signal and the output clock signal,

a second fine delay line circuit that receives the second coarse delay line circuit output signal and the phase detector output signal and generates the second delay line circuit output signal, and

a second buffer circuit that receives the second delay line circuit output signal and generates the output clock signal.

5. The zero delay buffer circuit of claim 4, wherein the first coarse delay line circuit comprises:

a coarse delay line having plurality of coarse delay cells that receive and delay the delayed modulated frequency clock signal and generate a corresponding plurality of coarse delay cell output signals; and

a multiplexer that receives the plurality of coarse delay cell output signals and the control signal to generate the first coarse delay line circuit output signal.

6. The zero delay buffer circuit of claim 4, wherein the second fine delay line circuit comprises a fine delay line having plurality of fine delay line cells that receive the coarse delay line circuit output signal and the phase detector output signal, delay the second coarse delay line output signal based on the phase detector output signal, and generate the second delay line circuit output signal.

7. The zero delay buffer circuit of claim 3, wherein the controller circuit comprises:

a plurality of lock detectors that receive the second output signal and the third output signals and generate corresponding lock detector output signals;

a logic circuit that receives the lock detector output signals and a delayed third output signal and generates a fourth output signal based on the lock detector output signals and the delayed third output signal; and

a counter that receives the fourth output signal and generates the control signal.

8. The zero delay buffer circuit of claim 7, wherein each of the lock detectors comprises:

a plurality of flip-flops that generate a plurality of fifth output signals, wherein each of the flip-flops receives the second output signal and one of the third output signals and generates one of the plurality of fifth output signals; and

a NOR logic gate that receives the fifth output signals and generates one of the corresponding lock detector output signals indicative of a delay between the second output signal and the third output signals, wherein the logic circuit is an AND logic gate.

9. A delay-locked loop (DLL) circuit, comprising:

a phase detector device that receives a modulated frequency clock signal and an output clock signal to generate phase detector output signals indicative of a phase difference between the modulated frequency clock signal and the output clock signal;

a charge pump circuit coupled to the phase detector device for receiving the phase detector output signals and generating charge pump signals;

a loop filter circuit receiving the charge pump signals;

a voltage controlled delay chain (VCDC) circuit coupled to the loop filter and the phase detector device, wherein the VCDC circuit aligns phases of the modulated frequency clock signal and the output clock signal;

a delayed pulse generator that receives and delays the modulated frequency clock signal to generate a delayed modulated frequency clock signal, and generates a first output signal and a second output signal based on the delayed modulated frequency clock signal;

a first delay line circuit that receives the first output signal, a control signal and a second delay line circuit output signal indicative of a delay between the output clock signal and the modulated frequency clock signal, and generates a plurality of third output signals controlled by the control signal, wherein the third output signals are indicative of the delay between the output clock signal and the delayed modulated frequency clock signal;

a controller circuit that receives the second output signal and the third output signals and generates the control signal, wherein the control signal is indicative of a delay between the second output signal and the third output signals; and

a second delay line circuit that receives the control signal, the modified frequency clock signal and the phase detector output signal to generate the output clock signal and the second delay line circuit output signal.

10. The DLL circuit of claim 9, wherein the phase detection device comprises:

a first phase detector circuit that receives the modulated frequency clock signal and generates first and second pulse signals indicative of one of a rising edge and a falling edge of the modulated frequency clock signal and the output clock signal, respectively;

a second phase detector circuit that receives the modulated frequency clock signal and generates third and fourth pulse signals indicative of one of the rising edge and the falling edge of the modulated frequency clock signal and the output clock signal, respectively; and

a signal divider circuit to alternatively operate the first and second phase detector circuit in one of an operational mode and a reset mode.

11. The DLL circuit of claim 10, wherein the first phase detector circuit comprises:

first and second logic gates, an output of the first logic gate being coupled to a first input of the second logic gate and a second input of the second logic gate being coupled to a first output of the signal divider circuit,

a first flip-flop coupled to a first input of the first logic gate, a constant signal, and an output of the second logic gate and responsive to the modulated frequency clock signal,

a second flip flop coupled to a second input of the first logic gate, the constant signal, and the output of the second logic gate and responsive to the output clock signal;

the second phase detector circuit comprises;

third and fourth logic gates, an output of the third logic gate being coupled to a first input of the fourth logic gate and a second input of the fourth logic gate being coupled to a second output of the signal divider circuit,

a third flip flop coupled to a first input of a third logic gate, the constant signal, and an output of the fourth logic gate and responsive to the modulated frequency clock signal,

a fourth flip flop coupled to a second input of the third logic gate, the constant signal, and the output of the fourth logic gate, and responsive to the output clock signal, and the signal divider circuit comprises a fifth flip-flop coupled to the modulated frequency clock signal and inputs of the second and fourth logic gates.

12. The DLL circuit of claim 11, wherein the first and third logic gates are AND logic gates, and the second and fourth logic gates are OR logic gates.

13. A method of generating an output clock signal having a reduced electromagnetic emission (EMI), comprising:

generating a modulated frequency clock signal based on spread spectrum modulation having an amplitude less than an amplitude of the input clock signal; and

aligning a phase of the modulated frequency clock signal with the output clock signal to eliminate phase differences between the output clock signal and the modulated frequency clock signal, wherein the aligning step comprises;

measuring a period of the modulated frequency clock signal to generate a first delayed modulated frequency clock signal;

measuring a period of the output clock signal;

generating a control signal indicative of a difference between the period of a digital signal that measures a time of the period of the first delayed modulated frequency clock signal, and a signal that measures a time of the period of the output clock signal;

delaying a phase of the modulated frequency clock signal based on the control signal to generate a second delayed modulated frequency clock signal;

detecting a phase difference between the modulated frequency clock signal and the output clock signal; and

aligning edges of the second delayed modulated frequency clock signal based on the phase difference.

14. A phase detection device, comprising:

a first phase detector circuit that receives a modulated frequency clock signal and generates first and second pulse signals indicative of one of a rising edge and a falling edge of the modulated frequency clock signal and an output clock signal, respectively;

a second phase detector circuit that receives the modulated frequency clock signal and generates third and fourth pulse signals indicative of one of the rising edge and the falling edge of the modulated frequency clock signal and the output clock signal, respectively; and

a signal divider circuit to alternatively operate the first and second phase detector circuits in one of an operational mode and a reset mode,

wherein the first phase detector circuit comprises;

first and second logic gates, an output of the first logic gate being coupled to a first input of the second logic gate and a second input of the second logic gate being coupled to a first output of the signal divider circuit,

a first flip-flop coupled to a first input of the first logic gate, a constant signal, and an output of the second logic gate and responsive to the modulated frequency clock signal,

a second flip-flop coupled to a second input of the first logic gate, the constant signal, and the output of the second logic gate and responsive to the output clock signal, and

wherein the second phase detector circuit comprises;

third and fourth logic gates, an output of the third logic gate being coupled to a first input of the fourth logic gate and a second input of the fourth logic gate being coupled to a second output of the signal divider circuit,

a third flip-flop coupled to a first input of a third logic gate, the constant signal, and an output of the fourth logic gate and responsive to the modulated frequency clock signal,

a fourth flip-flop coupled to a second input of the third logic gate, the constant signal, and the output of the fourth logic gate, and responsive to the output clock signal, and the signal divider circuit comprises a fifth flip-flop coupled to the modulated frequency clock signal and inputs of the second and fourth logic gates.

15. The phase detection device of claim 14, wherein the first gate and third logic gates are AND gates, and the second and fourth logic gates are OR gates.