Clock signal control device

• US 6,731,708 B1
• Filed: 12/16/1998
• Issued: 05/04/2004
• Est. Priority Date: 12/17/1997
• Status: Expired due to Term

• Current Assignee: Lenovo Innovations Ltd Hong Kong (Lenovo Group Ltd.)
• Original Assignee: NEC Corporation
• Inventors: Watanabe, Mitsuhiro
• Primary Examiner(s): Le, Amanda T.
• Application Number:
  US09/212,471
• Time in Patent Office: 1,966 Days
• Field of Search: 375/357, 327/291, 327/299, 327/142, 327/143, 327/160, 327/162, 327/165, 327/295, 713/300, 713/500, 713/502, 713/503
• US Class Current: 375/357
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: H03K 5/19 Monitoring patterns of pulse trains indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02

Abstract

Disclosed is a clock signal control device which has: an oscillator which generates a clock signal; a pulse detecting circuit which detects the frequency or duty of the clock signal and outputs a control signal based on the result of detection; and a clock signal supply selecting circuit which generates a supply clock signal from the clock signal generated from the oscillator in response to the control signal from the pulse detecting circuit.

Claims

1. A clock signal control device, comprising:

an oscillator which generates a clock signal;

a pulse detecting circuit which detects stability of the frequency or duty cycle of said clock signal and outputs a control signal based on the result of detection; and

a clock signal supply selecting circuit which generates a supply clock signal from said clock signal generated from said oscillator in response to said control signal from said pulse detecting circuit.

2. A clock signal control device, according to claim 1, wherein:

said pulse detecting circuit comprises;

a pulse voltage converter which outputs an output voltage corresponding to said duty of said clock signal; and

a voltage detector which outputs said control signal when said output voltage from said pulse voltage converter is higher than a predetermined level.

3. A clock signal control device, according to claim 2, wherein:

said voltage detector has hysteresis characteristic.

4. A clock signal control device, according to claim 3, wherein:

said pulse voltage converter comprises;

a pump circuit which charges a capacitor in response to said clock signal from said oscillator; and

an averaging circuit which outputs an analogue voltage corresponding to the voltage of said capacitor.

5. A clock signal control device, according to claim 3, wherein:

said pulse voltage converter comprises;

an averaging circuit which outputs an analogue voltage in response to said clock signal from said oscillator.

6. A clock signal control device, according to claim 3, wherein:

said clock signal supply selecting circuit comprises;

an AND gate circuit which calculates the logical addition between said control signal form said pulse detecting circuit and said clock signal from said oscillator and outputs the result of calculation as said supply clock signal.

7. A clock signal control device, according to claim 6, wherein:

said clock signal supply selecting circuit further comprises;

a synchronizing circuit which generates a synchronous control signal to synchronize with said clock signal of said oscillator from said control signal of said pulse detecting circuit;

wherein said AND gate circuit calculates the logical addition between said synchronous control signal, instead of said control signal from said pulse detecting circuit, and said clock signal of said oscillator, and outputs the result of calculation as said supply clock signal.

8. A clock signal control device, according to claim 3, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

9. A portable telephone, comprising said clock signal control device defined by claim 3.

10. A system, comprising a plurality of said clock signal control device defined by claim 3.

11. A clock signal control device, according to claim 10, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

12. A clock signal control device, according to claim 11, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

13. A clock signal control device, according to claim 10, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

14. A clock signal control device, according to claim 2, wherein:

said pulse voltage converter comprises;

a pump circuit which charges a capacitor in response to said clock signal from said oscillator; and

an averaging circuit which outputs an analogue voltage corresponding to the voltage of said capacitor.

15. A clock signal control device, according to claim 14, wherein:

said clock signal supply selecting circuit comprises;

an AND gate circuit which calculates the logical addition between said control signal form said pulse detecting circuit and said clock signal from said oscillator and outputs the result of calculation as said supply clock signal.

16. A clock signal control device, according to claim 15, wherein:

said clock signal supply selecting circuit further comprises;

a synchronizing circuit which generates a synchronous control signal to synchronize with said clock signal of said oscillator from said control signal of said pulse detecting circuit;

wherein said AND gate circuit calculates the logical addition between said synchronous control signal, instead of said control signal from said pulse detecting circuit, and said clock signal of said oscillator, and outputs the result of calculation as said supply clock signal.

17. A clock signal control device, according to claim 14, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

18. A portable telephone, comprising said clock signal control device defined by claim 14.

19. A system, comprising a plurality of said clock signal control device defined by claim 14.

20. A clock signal control device, according to claim 19, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

21. A clock signal control device, according to claim 20, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

22. A clock signal control device, according to claim 19, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

23. A clock signal control device, according to claim 2, wherein:

said pulse voltage converter comprises;

an averaging circuit which outputs an analogue voltage in response to said clock signal from said oscillator.

24. A clock signal control device, according to claim 23, wherein:

said clock signal supply selecting circuit comprises;

an AND gate circuit which calculates the logical addition between said control signal form said pulse detecting circuit and said clock signal from said oscillator and outputs the result of calculation as said supply clock signal.

25. A clock signal control device, according to claim 24, wherein:

said clock signal supply selecting circuit further comprises;

a synchronizing circuit which generates a synchronous control signal to synchronize with said clock signal of said oscillator from said control signal of said pulse detecting circuit;

wherein said AND gate circuit calculates the logical addition between said synchronous control signal, instead of said control signal from said pulse detecting circuit, and said clock signal of said oscillator, and outputs the result of calculation as said supply clock signal.

26. A clock signal control device, according to claim 23, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

27. A portable telephone, comprising said clock signal control device defined by claim 23.

28. A system, comprising a plurality of said clock signal control device defined by claim 23.

29. A clock signal control device, according to claim 28, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

30. A clock signal control device, according to claim 29, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

31. A clock signal control device, according to claim 28, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

32. A clock signal control device, according to claim 2, wherein:

said clock signal supply selecting circuit comprises;

an AND gate circuit which calculates the logical addition between said control signal form said pulse detecting circuit and said clock signal from said oscillator and outputs the result of calculation as said supply clock signal.

33. A clock signal control device, according to claim 32, wherein:

said clock signal supply selecting circuit further comprises;

a synchronizing circuit which generates a synchronous control signal to synchronize with said clock signal of said oscillator from said control signal of said pulse detecting circuit;

wherein said AND gate circuit calculates the logical addition between said synchronous control signal, instead of said control signal from said pulse detecting circuit, and said clock signal of said oscillator, and outputs the result of calculation as said supply clock signal.

34. A clock signal control device, according to claim 2, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

35. A portable telephone, comprising said clock signal control device defined by claim 2.

36. A system, comprising a plurality of said clock signal control device defined by claim 2.

37. A clock signal control device, according to claim 36, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

38. A clock signal control device, according to claim 37, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

39. A clock signal control device, according to claim 36, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

40. A clock signal control device, according to claim 1, wherein:

said pulse detecting circuit comprises;

a frequency counter which outputs an output voltage corresponding to the frequency of said clock signal; and

a frequency variation detector which outputs said control signal when said output voltage from said frequency counter is higher than a predetermined level.

41. A clock signal control device, according to claim 40, wherein:

said frequency counter comprises;

a one-shot multivibrator which generates a pulse in response to the pulse of said clock signal; and

an averaging circuit which generates an output voltage corresponding to the number of pulses generated by said one-shot multivibrator.

42. A clock signal control device, according to claim 41, wherein:

said clock signal supply selecting circuit comprises;

an AND gate circuit which calculates the logical addition between said control signal form said pulse detecting circuit and said clock signal from said oscillator and outputs the result of calculation as said supply clock signal.

43. A clock signal control device, according to claim 42, wherein:

said clock signal supply selecting circuit further comprises;

a synchronizing circuit which generates a synchronous control signal to synchronize with said clock signal of said oscillator from said control signal of said pulse detecting circuit;

wherein said AND gate circuit calculates the logical addition between said synchronous control signal, instead of said control signal from said pulse detecting circuit, and said clock signal of said oscillator, and outputs the result of calculation as said supply clock signal.

44. A clock signal control device, according to claim 41, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

45. A portable telephone, comprising said clock signal control device defined by claim 41.

46. A system, comprising a plurality of said clock signal control device defined by claim 41.

47. A clock signal control device, according to claim 46, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

48. A clock signal control device, according to claim 47, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

49. A clock signal control device, according to claim 46, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

50. A clock signal control device, according to claim 40, wherein:

said frequency variation detector comprises;

a differential circuit which differentiates said output voltage from said frequency counter;

a converter which converts the output of said differential circuit into a gate element level; and

a voltage detector which outputs said control signal when said output voltage from said frequency counter is higher than a predetermined level.

51. A clock signal control device, according to claim 50, wherein:

said voltage detector has hysteresis characteristic.

52. A clock signal control device, according to claim 51, wherein:

said clock signal supply selecting circuit comprises;

an AND gate circuit which calculates the logical addition between said control signal form said pulse detecting circuit and said clock signal from said oscillator and outputs the result of calculation as said supply clock signal.

53. A clock signal control device, according to claim 52, wherein:

said clock signal supply selecting circuit further comprises;

a synchronizing circuit which generates a synchronous control signal to synchronize with said clock signal of said oscillator from said control signal of said pulse detecting circuit;

wherein said AND gate circuit calculates the logical addition between said synchronous control signal, instead of said control signal from said pulse detecting circuit, and said clock signal of said oscillator, and outputs the result of calculation as said supply clock signal.

54. A clock signal control device, according to claim 51, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

55. A portable telephone, comprising said clock signal control device defined by claim 51.

56. A system, comprising a plurality of said clock signal control device defined by claim 51.

57. A clock signal control device, according to claim 56, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

58. A clock signal control device, according to claim 57, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

59. A clock signal control device, according to claim 56, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

60. A clock signal control device, according to claim 50, wherein:

said clock signal supply selecting circuit comprises;

an AND gate circuit which calculates the logical addition between said control signal form said pulse detecting circuit and said clock signal from said oscillator and outputs the result of calculation as said supply clock signal.

61. A clock signal control device, according to claim 60, wherein:

said clock signal supply selecting circuit further comprises;

a synchronizing circuit which generates a synchronous control signal to synchronize with said clock signal of said oscillator from said control signal of said pulse detecting circuit;

wherein said AND gate circuit calculates the logical addition between said synchronous control signal, instead of said control signal from said pulse detecting circuit, and said clock signal of said oscillator, and outputs the result of calculation as said supply clock signal.

62. A clock signal control device, according to claim 50, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

63. A portable telephone, comprising said clock signal control device defined by claim 50.

64. A system, comprising a plurality of said clock signal control device defined by claim 50.

65. A clock signal control device, according to claim 64, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

66. A clock signal control device, according to claim 65, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

67. A clock signal control device, according to claim 64, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

68. A clock signal control device, according to claim 40, wherein:

said clock signal supply selecting circuit comprises;

an AND gate circuit which calculates the logical addition between said control signal form said pulse detecting circuit and said clock signal from said oscillator and outputs the result of calculation as said supply clock signal.

69. A clock signal control device, according to claim 68, wherein:

said clock signal supply selecting circuit further comprises;

a synchronizing circuit which generates a synchronous control signal to synchronize with said clock signal of said oscillator from said control signal of said pulse detecting circuit;

wherein said AND gate circuit calculates the logical addition between said synchronous control signal, instead of said control signal from said pulse detecting circuit, and said clock signal of said oscillator, and outputs the result of calculation as said supply clock signal.

70. A clock signal control device, according to claim 40, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

71. A portable telephone, comprising said clock signal control device defined by claim 40.

72. A system, comprising a plurality of said lock signal control device defined by claim 40.

73. A clock signal control device, according to claim 72, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

74. A clock signal control device, according to claim 73, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

75. A clock signal control device, according to claim 72, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

76. A clock signal control device, according to claim 1, wherein:

said clock signal supply selecting circuit comprises;

an AND gate circuit which calculates the logical addition between said control signal from said pulse detecting circuit and said clock signal from said oscillator and outputs the result of calculation as said supply clock signal.

77. A clock signal control device, according to claim 76, wherein:

said clock signal supply selecting circuit further comprises;

a synchronizing circuit which generates a synchronous control signal to synchronize with said clock signal of said oscillator from said control signal of said pulse detecting circuit;

wherein said AND gate circuit calculates the logical addition between said synchronous control signal, instead of said control signal from said pulse detecting circuit, and said clock signal of said oscillator, and outputs the result of calculation as said supply clock signal.

78. A clock signal control device, according to claim 77, wherein:

said synchronizing circuit is enabled to operate by a reset signal.

79. A clock signal control device, according to claim 78, wherein:

said clock signal supply selecting circuit further comprises;

a reset circuit which is enabled to operate in response to said reset signal and outputs said clock signal of said oscillator as a supply reset signal while delaying it.

80. A clock signal control device, according to claim 79, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

81. A portable telephone, comprising said clock signal control device defined by claim 79.

82. A system, comprising a plurality of said clock signal control device defined by claim 79.

83. A clock signal control device, according to claim 82, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

84. A clock signal control device, according to claim 78, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

85. A clock signal control device, according to claim 83, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

86. A clock signal control device, according to claim 82, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

87. A portable telephone, comprising said clock signal control device defined by claim 78.

88. A system, comprising a plurality of said clock signal control device defined by claim 78.

89. A clock signal control device, according to claim 88, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

90. A clock signal control device, according to claim 89, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

91. A clock signal control device, according to claim 88, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

92. A clock signal control device, according to claim 77, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

93. A portable telephone, comprising said clock signal control device defined by claim 77.

94. A system, comprising a plurality of said clock signal control device defined by claim 77.

95. A clock signal control device, according to claim 94, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

96. A clock signal control device, according to claim 95, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

97. A clock signal control device, according to claim 94, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

98. A clock signal control device, according to claim 76, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

99. A portable telephone, comprising said clock signal control device defined by claim 76.

100. A system, comprising a plurality of said clock signal control device defined by claim 76.

101. A clock signal control device, according to claim 100, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

102. A clock signal control device, according to claim 101, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

103. A clock signal control device, according to claim 100, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

104. A clock signal control device, according to claim 1, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

105. A portable telephone, comprising said clock signal control device defined by claim 104.

106. A portable telephone, comprising said clock signal control device defined by claim 1.

107. A system, comprising a plurality of said clock signal control device defined by claim 1.

108. A clock signal control device, according to claim 107, wherein:

said oscillator comprises;

an oscillation circuit which conducts electrical oscillation; and

a frequency doubling circuit which doubles the frequency of said oscillation circuit.

109. A clock signal control device, according to claim 108, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.

110. A clock signal control device, according to claim 107, wherein:

at least one of said plurality of clock signal control device comprises a frequency-dividing circuit which frequency-divides said clock signal from said oscillator and outputs the frequency-divided clock signal to said pulse detecting circuit.