Fully integrated broadband tuner
First Claim
1. A phase-locked loop frequency synthesizer comprising:
- a phase/frequency detector that compares a reference frequency with an output frequency signal and generates an appropriate charge pump control voltage;
a programmable charge pump coupled to said phase/frequency detector that generates a loop filter control current from the charge pump control voltage;
a loop filter coupled to said charge pump that generates a loop filter voltage;
an oscillator bank coupled to the loop filter comprising a plurality of voltage controlled oscillators;
a feedback circuit coupled between said oscillator bank and said phase/frequency detector that provides the output frequency to the phase/frequency detector; and
a logic interface coupled to said oscillator bank for enabling one of said voltage controlled oscillators at a time, and coupled to the charge pump for programming the output current and output polarity of the charge pump as required by the enabled voltage controlled oscillator.
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Abstract
A fully integrated single-loop frequency synthesizer, which can serve as a local oscillator for a broadband tuner, is disclosed, thus allowing the creation of a single-chip solution for broadband applications. The tank circuits are integrated into the tuner chip through the combination of a phase-locked loop and multiple on-chip VCOs comprising narrow-tuning range varactors. Drift in the VCOs caused by heat is overcome by designing the VCOs to overlap each other. Initial tolerance problems associated with the VCOs are overcome by the use of a calibration method. The calibration of the VCOs is accomplished by utilizing the lock detect output of the phase-locked loop and a binary search algorithm. The edges of each VCO are determined with this calibration method, thereby enabling VCO selection based on the desired channel. A sufficient number of VCOs are provided such that whatever the initial tolerance shift, the full broadband spectrum can still be covered after calibration. Additionally, the problem of coupling between the local oscillator signal and the incoming radio frequency signal is mediated by the use of a programmable 2/4 divider. This 2/4 divider also provides additional flexibility in choosing the number of VCOs to put on the chip and which VCO to use in a particular implementation.
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Citations
26 Claims
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1. A phase-locked loop frequency synthesizer comprising:
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a phase/frequency detector that compares a reference frequency with an output frequency signal and generates an appropriate charge pump control voltage;
a programmable charge pump coupled to said phase/frequency detector that generates a loop filter control current from the charge pump control voltage;
a loop filter coupled to said charge pump that generates a loop filter voltage;
an oscillator bank coupled to the loop filter comprising a plurality of voltage controlled oscillators;
a feedback circuit coupled between said oscillator bank and said phase/frequency detector that provides the output frequency to the phase/frequency detector; and
a logic interface coupled to said oscillator bank for enabling one of said voltage controlled oscillators at a time, and coupled to the charge pump for programming the output current and output polarity of the charge pump as required by the enabled voltage controlled oscillator. - View Dependent Claims (2, 3)
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4. A local oscillator integrated on a single semiconductor chip having a reference frequency input and a frequency output, comprising:
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a phase-locked loop for comparing the difference in phase between the reference frequency input and the frequency output of the local oscillator, wherein said phase-locked loop includes an oscillator bank;
said oscillator bank comprising a plurality of voltage controlled oscillators connected in parallel; and
a logic interface coupled to said oscillator bank for enabling one of said voltage controlled oscillators at a time. - View Dependent Claims (5, 6, 7)
a frequency divider coupled to the reference frequency input and said phase-locked loop for dividing the reference frequency input to obtain a new reference frequency; and
said logic interface is coupled to said frequency divider for enabling programming of the new reference frequency.
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6. The local oscillator of claim 4, wherein said phase-locked loop includes a frequency divider for changing the frequency output before comparison with the reference frequency input, and wherein said logic interface is coupled to said frequency divider for enabling programming of the output frequency.
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7. The local oscillator of claim 4, wherein said phase-locked loop includes a loop filter implemented by a line out to off-chip capacitors and resistors.
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8. A direct down-conversion broadband tuner integrated on a single semiconductor chip comprising:
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at least one mixer;
at least one low pass filter;
at least one amplifier; and
a local oscillator comprising;
a phase-locked loop for comparing the difference in phase between a reference frequency input and a frequency output from the local oscillator, wherein said phase-locked loop includes an oscillator bank and a frequency divider for changing the frequency output before comparison with the reference frequency input;
a reference frequency divider coupled to the reference frequency input and said phase-locked loop for dividing the reference frequency input to obtain a new reference frequency;
said oscillator bank comprising a plurality of voltage controlled oscillators connected in parallel; and
a logic interface coupled to said phase-locked loop for enabling one of said voltage controlled oscillators at a time, coupled to said frequency divider for enabling programming of the frequency output based on the enabled voltage controlled oscillator, and coupled to the reference frequency divider for enabling programming of the new reference frequency based on the enabled voltage controlled oscillator. - View Dependent Claims (9)
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10. A method for providing a local oscillator integrated on a single semiconductor chip for use in a broadband tuner, comprising the steps of:
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providing a phase-locked loop having an oscillator bank comprising a plurality of voltage controlled oscillators;
connecting a logic interface to the oscillator bank such that each of the voltage controlled oscillators can be selectively enabled to the exclusion of the other voltage controlled oscillators; and
programming the logic interface such that an appropriate voltage controlled oscillator is enabled when a carrier frequency is selected. - View Dependent Claims (11, 12, 13)
providing a reference frequency divider coupled to the phase-locked loop input;
connecting the logic interface to the reference frequency divider; and
programming the logic interface to select an appropriate number to supply to the reference frequency divider based on the input reference frequency and the selected carrier frequency.
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13. The method of claim 12, further comprising the step of:
calibrating the oscillator bank to determine the appropriate number to supply to the reference frequency divider, the appropriate number to supply to the frequency divider and the appropriate voltage controlled oscillator to enable, based upon a set of carrier frequencies and the input reference frequency.
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14. A method for providing a broadband tuner integrated on a single semiconductor chip comprising the steps of:
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supplying at least one mixer, at least one low-pass filter and at least one amplifier;
providing a phase-locked loop having an oscillator bank comprising a plurality of voltage-controlled oscillators;
connecting a logic interface to the oscillator bank such that each of the voltage controlled oscillators can be selectively enabled to the exclusion of the other voltage controlled oscillators; and
programming the logic interface such that an appropriate voltage controlled oscillator is enabled when a carrier frequency is selected. - View Dependent Claims (15, 16, 17, 18, 19)
providing a reference frequency divider coupled to the phase-locked loop input;
connecting the logic interface to the reference frequency divider; and
programming the logic interface to select an appropriate number to supply to the reference Frequency divider based on the input reference frequency and the selected carrier frequency.
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17. The method of claim 16, further comprising the-step of:
calibrating the local oscillator bank to determine the appropriate number to supply to the reference frequency divider, the appropriate number to supply to the frequency divider and the appropriate voltage controlled oscillator to enable, based upon a set of carrier frequencies and the input reference frequency.
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18. The method of claim 16, further comprising the steps of:
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supplying a local oscillator output divider coupled to the mixer and the local oscillator;
connecting the logic interface to the local oscillator output divider; and
programming the logic interface to select an appropriate number to supply to the local oscillator output divider based on the input reference frequency and the selected carrier frequency.
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19. The method of claim 18, further comprising the step of:
calibrating the oscillator bank to determine the appropriate number to supply to the reference frequency divider, the appropriate number to supply to the frequency divider, the appropriate number to supply to the local oscillator output divider and the appropriate voltage controlled oscillator to enable, based on a set of carrier frequencies and-the input reference frequency.
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20. A circuit comprising:
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a detector generating a first signal in response to a difference between a reference frequency and an output frequency signal;
a charge pump coupled with said detector generating a second signal in response to said first signal;
a filter coupled with said charge pump that generates a third signal;
an oscillator bank coupled with said filter, said oscillator bank comprising at least two oscillators integrated on a single chip;
a divider coupled with said oscillator bank and with said detector, said divider providing the output frequency signal to said detector; and
an interface coupled with said oscillator bank that selects one of said at least two oscillators. - View Dependent Claims (21, 22, 23, 24, 25, 26)
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Specification