Determination of transmitter distortion

• US 6,731,914 B2
• Filed: 02/22/2001
• Issued: 05/04/2004
• Est. Priority Date: 11/02/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Creigh, John L., Agazzi, Oscar E.
• Primary Examiner(s): Trinh, Sonny
• Application Number:
  US09/792,763
• Publication Number:
  US 20010034216A1
• Time in Patent Office: 1,167 Days
• Field of Search: 455/115.1, 455/91, 455/501, 455/115.2, 455/67.11, 455/67.14, 455/63.1, 455/126, 455/114.2, 375/278, 375/285, 375/295, 375/296, 375/284, 375/297, 375/146, 324/314
• US Class Current: 455/115.1
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/3008 Quiescent current [IDDQ] test or leakage current test
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G01R 31/318502 Test of Combinational circuits
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03369 Partial response
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03496 as a prediction filter
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 2025/03745 Timing of adaptation
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 : with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03267 : with decision feedback equalisers
• CPC Class Codes: H04L 25/067 : providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 25/14 : Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 25/497 : by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 7/0062 : detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0334 : Processing of samples having at least three levels, e.g. soft decisions

Abstract

The present invention provides a method for determining nonlinear distortion of a transmitter. A test symbol sequence is transmitted from the transmitter under test as an analog output signal. The analog output signal is sampled to produce a first sequence which represents the test symbol sequence as distorted by a linear distortion sequence and a nonlinear distortion sequence. The test symbol sequence is filtered via an adaptive filter to produce a second sequence such that the second sequence is approximately equal to the test symbol sequence as distorted by the linear distortion sequence. The second sequence is subtracted from the first sequence to produce an output sequence substantially equal to the nonlinear distortion sequence.

Claims

1. A symbol generator for generating a test symbol sequence S(n) for measuring nonlinear distortion of a transmitter under test, characterized by:

a shift register for generating a set of bit sequences; and

a symbol mapper for mapping the bit sequences to the test symbol sequence;

wherein the shift register is further characterized by;

a linear feedback shift register having eleven delay elements to implement the generator polynomial;

g(s)=1+x⁹+x¹¹ in GF(2), wherein GF(2) denotes the Galois field of 2, the generator polynomial outputting a pseudo-random bit sequence x0_n generated according to g(x), with subscript n denoting a time index, the linear feedback shift register being updated once per symbol period and at each symbol period the linear feedback shift register being advanced by one bit and one new bit of sequence x0_n being generated, the linear feedback register providing two additional pseudo-random bit sequences x1_n and x2_n being generated by the linear combinations of time delayed versions of x0_n, wherein;

2. A system for determining nonlinear distortion of a transmitter, the system characterized by:

(a) the transmitter transmitting a test symbol sequence S(n), generated for measuring nonlinear distortion of a transmitter under test, as an analog output signal;

(b) a sampler sampling the analog output signal to produce a first sequence, the first sequence representing a combination of the test symbol sequence, a linear distortion sequence and a nonlinear distortion sequence;

(c) an adaptive filter filtering at least a portion of the nonlinear distortion sequence from the first sequence to produce a second sequence;

(d) an adder combining the first sequence and the second sequence; and

(e) wherein the transmitter is further characterized by a symbol generator for generating the test symbol sequence, wherein the symbol generator is further characterized by;

a symbol mapper for mapping the bit sequences to the test symbol sequence; and

a shift register for generating a set of bit sequences, wherein the shift register is further characterized by;

a linear feedback shift register having eleven delay elements to implement the generator polynomial;

g(s)=1+x⁹+x¹¹ in GF(2), wherein GF(2) denotes the Galois field of 2, the generator polynomial outputting a pseudo-random bit sequence x0_n generated according to g(x), with subscript n denoting a time index;

the linear feedback shift register being updated once per symbol period and at each symbol period the linear feedback shift register being advanced by one bit and one new bit of sequence x0_n being generated;

the linear feedback register providing two additional pseudo-random bit sequences x1_n and x2_n being generated by the linear combinations of time delayed versions of x0_n, wherein;