Memory circuit for use in hardware emulation system

• US 6,732,068 B2
• Filed: 08/02/2001
• Issued: 05/04/2004
• Est. Priority Date: 05/30/1997
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Bershteyn, Mikhail, Butts, Michael R., Bauer, Jerry R., Sample, Stephen P.
• Primary Examiner(s): Thomson, W.
• Assistant Examiner(s): DAY, HERNG DER
• Application Number:
  US09/922,113
• Publication Number:
  US 20020161568A1
• Time in Patent Office: 1,006 Days
• Field of Search: 703/24, 703/25, 703/27, 703/28, 703/23, 326/40, 712/14, 712/15, 712/16, 712/11
• US Class Current: 703/24
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: Y10S 370/916 Multiplexer/demultiplexer

Abstract

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Claims

1. A programmable memory circuit implemented in at least one programmable logic device of a hardware logic emulation system for implementing user memories having at least one read port and at least one write port, the at least one programmable logic device comprising configurable logic elements having random access memory (RAM) components, the programmable memory circuit comprising:

an arbitrator for prioritizing write operations of the memory circuit when there are requests from a plurality of ports, said arbitrator outputting a first signal;

a read counter, said read counter outputting a second signal;

a first multiplexer, said first multiplexer having a first data input and a second data input, said first data input receiving said first signal, said second data input receiving said second signal, said first multiplexer outputting a third signal;

at least one data multiplexer for receipt of data to be stored, said data multiplexer having a select input in electrical communication with said third signal;

a plurality of address multiplexers, said plurality of address multiplexers comprising read address multiplexers and write address multiplexers, said read address multiplexers programmed to receive any read address data, said write address multiplexers programmed to receive any write address data, said read address multiplexers and said write address multiplexers having select inputs in electrical communication with said third signal;

a memory circuit programmed into the configurable logic elements of the at least one programmable logic device, said memory circuit receiving data from said data multiplexer, said memory circuit receiving read address information from said read address multiplexers, said memory circuit receiving write address information from said write address multiplexers;

a decoder having said third signal as its input; and

at least one output register, said at least one output registers receiving data from said memory circuit and clock enable signals from said decoder.

2. The memory circuit of claim 1 wherein said first signal comprises a write address/data multiplexer select signal and a write enable signal.

3. The memory circuit of claim 1 wherein said read counter cycles through the at least one read ports of the user memory.

4. The memory circuit of claim 1 wherein said third signal comprises a signal for selecting one of the at least one read port or the at least one write port of the user memory.